sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'

Browse Source 
Change-Id: I1a70eea8c4f835e5673e75282c9cecb24b150e3d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2020-08-12 09:50:48 +02:00 committed by Patrick Georgi
parent eaa165dfb4
commit 27ce8e3296
1 changed files with 2 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/southbridge/intel/lynxpoint/early_pch.c
View File

@ -6,6 +6,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/smbus_host.h> #include <device/smbus_host.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/common/pmclib.h>
#include <elog.h> #include <elog.h>
#include "pch.h" #include "pch.h"
@ -57,7 +58,7 @@ static void pch_generic_setup(void)
{ {
printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ write_pmbase16(0x60 | 0x08, (1 << 11)); /* halt timer */
printk(BIOS_DEBUG, " done.\n"); printk(BIOS_DEBUG, " done.\n");
} }