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device/resource: Add _kb postfix for resource allocators

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There is a lot of going back-and-forth with the KiB arguments, start
the work to migrate away from this.

Change-Id: I329864d36137e9a99b5640f4f504c45a02060a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64658
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2022-05-24 20:25:58 +03:00
parent 37b161fb96
commit 27d6299d51
78 changed files with 256 additions and 256 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/mtrr/amd_mtrr.c
View File

@ -19,5 +19,5 @@ void add_uma_resource_below_tolm(struct device *nb, int idx)
printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
__func__, uma_size, uma_base);
uma_resource(nb, idx, uma_base / KiB, uma_size / KiB);
uma_resource_kb(nb, idx, uma_base / KiB, uma_size / KiB);
}

2
src/device/device_util.c
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@ -822,7 +822,7 @@ void show_all_devs_resources(int debug_level, const char *msg)
}
}
void fixed_mem_resource(struct device *dev, unsigned long index,
void fixed_mem_resource_kb(struct device *dev, unsigned long index,
unsigned long basek, unsigned long sizek,
unsigned long type)
{

2
src/drivers/aspeed/ast2050/ast2050.c
View File

@ -14,7 +14,7 @@
static void aspeed_ast2050_read_resources(struct device *dev)
{
/* Reserve VGA regions */
mmio_resource(dev, 3, 0xa0000 >> 10, 0x1ffff >> 10);
mmio_resource_kb(dev, 3, 0xa0000 >> 10, 0x1ffff >> 10);
/* Run standard resource read routine */
pci_dev_read_resources(dev);

2
src/drivers/pc80/tpm/tis.c
View File

@ -749,7 +749,7 @@ static int tis_setup_interrupt(int vector, int polarity)
static void lpc_tpm_read_resources(struct device *dev)
{
/* Static 5K memory region specified in Kconfig */
mmio_resource(dev, 0, CONFIG_TPM_TIS_BASE_ADDRESS >> 10, 0x5000 >> 10);
mmio_resource_kb(dev, 0, CONFIG_TPM_TIS_BASE_ADDRESS >> 10, 0x5000 >> 10);
}
static void lpc_tpm_set_resources(struct device *dev)

26
src/include/device/device.h
View File

@ -310,29 +310,29 @@ void pci_domain_scan_bus(struct device *dev);
void fixed_io_resource(struct device *dev, unsigned long index,
unsigned long base, unsigned long size);
void fixed_mem_resource(struct device *dev, unsigned long index,
void fixed_mem_resource_kb(struct device *dev, unsigned long index,
unsigned long basek, unsigned long sizek, unsigned long type);
void mmconf_resource(struct device *dev, unsigned long index);
/* It is the caller's responsibility to adjust regions such that ram_resource()
* and mmio_resource() do not overlap.
/* It is the caller's responsibility to adjust regions such that ram_resource_kb()
* and mmio_resource_kb() do not overlap.
*/
#define ram_resource(dev, idx, basek, sizek) \
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
#define ram_resource_kb(dev, idx, basek, sizek) \
fixed_mem_resource_kb(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
#define reserved_ram_resource(dev, idx, basek, sizek) \
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE \
#define reserved_ram_resource_kb(dev, idx, basek, sizek) \
fixed_mem_resource_kb(dev, idx, basek, sizek, IORESOURCE_CACHEABLE \
| IORESOURCE_RESERVE)
#define bad_ram_resource(dev, idx, basek, sizek) \
reserved_ram_resource((dev), (idx), (basek), (sizek))
#define bad_ram_resource_kb(dev, idx, basek, sizek) \
reserved_ram_resource_kb((dev), (idx), (basek), (sizek))
#define uma_resource(dev, idx, basek, sizek) \
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE)
#define uma_resource_kb(dev, idx, basek, sizek) \
fixed_mem_resource_kb(dev, idx, basek, sizek, IORESOURCE_RESERVE)
#define mmio_resource(dev, idx, basek, sizek) \
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_RESERVE)
#define mmio_resource_kb(dev, idx, basek, sizek) \
fixed_mem_resource_kb(dev, idx, basek, sizek, IORESOURCE_RESERVE)
#define io_resource(dev, idx, base, size) \
fixed_io_resource(dev, idx, base, size)

2
src/mainboard/emulation/qemu-aarch64/mainboard.c
View File

@ -13,7 +13,7 @@ void bootmem_platform_add_ranges(void)
static void mainboard_enable(struct device *dev)
{
int ram_size_mb = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB);
ram_resource(dev, 0, (uintptr_t)_dram / KiB, ram_size_mb * KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, ram_size_mb * KiB);
}
struct chip_operations mainboard_ops = {

2
src/mainboard/emulation/qemu-armv7/mainboard.c
View File

@ -39,7 +39,7 @@ static void mainboard_enable(struct device *dev)
discovered = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB);
printk(BIOS_DEBUG, "%d MiB of RAM discovered\n", discovered);
ram_resource(dev, 0, 0x60000000 >> 10, discovered << 10);
ram_resource_kb(dev, 0, 0x60000000 >> 10, discovered << 10);
init_gfx();
}

2
src/mainboard/emulation/qemu-i440fx/mainboard.c
View File

@ -37,7 +37,7 @@ static void qemu_nb_read_resources(struct device *dev)
if (CONFIG(ARCH_RAMSTAGE_X86_64)) {
/* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */
reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB,
reserved_ram_resource_kb(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB,
(6 * 0x1000) / KiB);
}
}

16
src/mainboard/emulation/qemu-i440fx/northbridge.c
View File

@ -65,10 +65,10 @@ static void cpu_pci_domain_read_resources(struct device *dev)
list[i].address, list[i].length);
if (list[i].address == 0) {
tomk = list[i].length / 1024;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768);
ram_resource_kb(dev, idx++, 0, 640);
ram_resource_kb(dev, idx++, 768, tomk - 768);
} else {
ram_resource(dev, idx++,
ram_resource_kb(dev, idx++,
list[i].address / 1024,
list[i].length / 1024);
}
@ -99,10 +99,10 @@ static void cpu_pci_domain_read_resources(struct device *dev)
printk(BIOS_DEBUG, "QEMU: cmos: %lu MiB RAM above 4G.\n", high / 1024);
/* Report the memory regions. */
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768);
ram_resource_kb(dev, idx++, 0, 640);
ram_resource_kb(dev, idx++, 768, tomk - 768);
if (high)
ram_resource(dev, idx++, 4 * 1024 * 1024, high);
ram_resource_kb(dev, idx++, 4 * 1024 * 1024, high);
}
/* Reserve I/O ports used by QEMU */
@ -119,10 +119,10 @@ static void cpu_pci_domain_read_resources(struct device *dev)
}
/* A segment is legacy VGA region */
mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
/* C segment to 1MB is reserved RAM (low tables) */
reserved_ram_resource(dev, idx++, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
if (q35 && ((tomk * 1024) < 0xb0000000)) {
/*

2
src/mainboard/emulation/qemu-power8/mainboard.c
View File

@ -11,7 +11,7 @@ static void mainboard_enable(struct device *dev)
}
/* Where does RAM live? */
ram_resource(dev, 0, 2048, 32768);
ram_resource_kb(dev, 0, 2048, 32768);
}
struct chip_operations mainboard_ops = {

2
src/mainboard/emulation/qemu-power9/mainboard.c
View File

@ -8,7 +8,7 @@ static void mainboard_enable(struct device *dev)
{
if (!dev)
die("No dev0; die\n");
ram_resource(dev, 0, 0, (unsigned long)cbmem_top() / KiB);
ram_resource_kb(dev, 0, 0, (unsigned long)cbmem_top() / KiB);
}
struct chip_operations mainboard_ops = {

4
src/mainboard/emulation/qemu-q35/mainboard.c
View File

@ -55,12 +55,12 @@ static void qemu_nb_read_resources(struct device *dev)
if (CONFIG(ARCH_RAMSTAGE_X86_64)) {
/* Reserve page tables in DRAM. FIXME: Remove once x86_64 page tables reside in CBMEM */
reserved_ram_resource(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB,
reserved_ram_resource_kb(dev, 0, CONFIG_ARCH_X86_64_PGTBL_LOC / KiB,
(6 * 0x1000) / KiB);
}
smm_region(&tseg_base, &tseg_size);
reserved_ram_resource(dev, ESMRAMC, tseg_base / 1024, tseg_size / 1024);
reserved_ram_resource_kb(dev, ESMRAMC, tseg_base / 1024, tseg_size / 1024);
}

2
src/mainboard/emulation/qemu-riscv/mainboard.c
View File

@ -14,7 +14,7 @@ static void mainboard_enable(struct device *dev)
}
dram_mb_detected = probe_ramsize((uintptr_t)_dram, CONFIG_DRAM_SIZE_MB);
ram_resource(dev, 0, (uintptr_t)_dram / KiB, dram_mb_detected * MiB / KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, dram_mb_detected * MiB / KiB);
}
struct chip_operations mainboard_ops = {

2
src/mainboard/emulation/spike-riscv/mainboard.c
View File

@ -17,7 +17,7 @@ static void mainboard_enable(struct device *dev)
die("No dev0; die\n");
}
ram_resource(dev, 0, 0x80000000/KiB, ram_size/KiB);
ram_resource_kb(dev, 0, 0x80000000/KiB, ram_size/KiB);
}
struct chip_operations mainboard_ops = {

2
src/mainboard/sifive/hifive-unleashed/mainboard.c
View File

@ -6,7 +6,7 @@
static void mainboard_enable(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*KiB);
}
struct chip_operations mainboard_ops = {

6
src/northbridge/amd/agesa/family14/northbridge.c
View File

@ -554,7 +554,7 @@ static void domain_set_resources(struct device *dev)
/* See if we need a hole from 0xa0000 (640K) to 0xbffff (768K) */
if (basek < 640 && sizek > 768) {
printk(BIOS_DEBUG,"adsr - 0xa0000 to 0xbffff resource.\n");
ram_resource(dev, (idx | 0), basek, 640 - basek);
ram_resource_kb(dev, (idx | 0), basek, 640 - basek);
idx += 0x10;
basek = 768;
sizek = limitk - basek;
@ -570,7 +570,7 @@ static void domain_set_resources(struct device *dev)
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, idx, basek,
ram_resource_kb(dev, idx, basek,
pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@ -585,7 +585,7 @@ static void domain_set_resources(struct device *dev)
}
}
ram_resource(dev, (idx | 0), basek, sizek);
ram_resource_kb(dev, (idx | 0), basek, sizek);
idx += 0x10;
printk(BIOS_DEBUG,
"%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", 0,

6
src/northbridge/amd/agesa/family15tn/northbridge.c
View File

@ -711,7 +711,7 @@ static void domain_set_resources(struct device *dev)
/* See if we need a hole from 0xa0000 (640K) to 0xbffff (768K) */
if (basek < 640 && sizek > 768) {
ram_resource(dev, (idx | i), basek, 640 - basek);
ram_resource_kb(dev, (idx | i), basek, 640 - basek);
idx += 0x10;
basek = 768;
sizek = limitk - basek;
@ -724,7 +724,7 @@ static void domain_set_resources(struct device *dev)
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
ram_resource_kb(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
}
@ -740,7 +740,7 @@ static void domain_set_resources(struct device *dev)
}
}
ram_resource(dev, (idx | i), basek, sizek);
ram_resource_kb(dev, (idx | i), basek, sizek);
idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);

6
src/northbridge/amd/agesa/family16kb/northbridge.c
View File

@ -723,7 +723,7 @@ static void domain_set_resources(struct device *dev)
/* See if we need a hole from 0xa0000 (640K) to 0xbffff (768K) */
if (basek < 640 && sizek > 768) {
ram_resource(dev, (idx | i), basek, 640 - basek);
ram_resource_kb(dev, (idx | i), basek, 640 - basek);
idx += 0x10;
basek = 768;
sizek = limitk - basek;
@ -737,7 +737,7 @@ static void domain_set_resources(struct device *dev)
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
ram_resource_kb(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
}
@ -753,7 +753,7 @@ static void domain_set_resources(struct device *dev)
}
}
ram_resource(dev, (idx | i), basek, sizek);
ram_resource_kb(dev, (idx | i), basek, sizek);
idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);

12
src/northbridge/amd/pi/00730F01/northbridge.c
View File

@ -139,8 +139,8 @@ static void add_fixed_resources(struct device *dev, int index)
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xfffff: option ROMs and SeaBIOS (if used)
*/
mmio_resource(dev, index++, 0xa0000 >> 10, (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
mmio_resource_kb(dev, index++, 0xa0000 >> 10, (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
if (fx_devs == 0)
get_fx_devs();
@ -151,7 +151,7 @@ static void add_fixed_resources(struct device *dev, int index)
resource_t basek, limitk;
if (!get_dram_base_limit(0, &basek, &limitk))
return;
mmio_resource(dev, index++, limitk, 16*1024);
mmio_resource_kb(dev, index++, limitk, 16*1024);
}
}
@ -812,7 +812,7 @@ static void domain_read_resources(struct device *dev)
/* See if we need a hole from 0xa0000 (640K) to 0xfffff (1024K) */
if (basek < 640 && sizek > 1024) {
ram_resource(dev, (idx | i), basek, 640 - basek);
ram_resource_kb(dev, (idx | i), basek, 640 - basek);
idx += 0x10;
basek = 1024;
sizek = limitk - basek;
@ -827,7 +827,7 @@ static void domain_read_resources(struct device *dev)
unsigned int pre_sizek;
pre_sizek = mmio_basek - basek;
if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
ram_resource_kb(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
}
@ -843,7 +843,7 @@ static void domain_read_resources(struct device *dev)
}
}
ram_resource(dev, (idx | i), basek, sizek);
ram_resource_kb(dev, (idx | i), basek, sizek);
idx += 0x10;
printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
i, mmio_basek, basek, limitk);

8
src/northbridge/intel/e7505/northbridge.c
View File

@ -39,14 +39,14 @@ static void mch_domain_read_resources(struct device *dev)
/* Report the memory regions */
idx = 10;
ram_resource(dev, idx++, 0, tolmk);
mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
ram_resource_kb(dev, idx++, 0, tolmk);
mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
if (tomk > basek_4G)
ram_resource(dev, idx++, basek_4G, tomk - basek_4G);
ram_resource_kb(dev, idx++, basek_4G, tomk - basek_4G);
if (remaplimitk > remapbasek)
ram_resource(dev, idx++, remapbasek, remaplimitk - remapbasek);
ram_resource_kb(dev, idx++, remapbasek, remaplimitk - remapbasek);
}
static void mch_domain_set_resources(struct device *dev)

14
src/northbridge/intel/gm45/northbridge.c
View File

@ -103,7 +103,7 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
/* Report lowest memory region */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
/*
* Reserve everything between A segment and 1MB:
@ -111,11 +111,11 @@ static void mch_domain_read_resources(struct device *dev)
* 0xa0000 - 0xbffff: Legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
reserved_ram_resource(dev, idx++, 0xc0000 / KiB, (1*MiB - 0xc0000) / KiB);
mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, (1*MiB - 0xc0000) / KiB);
/* Report < 4GB memory */
ram_resource(dev, idx++, 1*MiB / KiB, tomk - 1*MiB / KiB);
ram_resource_kb(dev, idx++, 1*MiB / KiB, tomk - 1*MiB / KiB);
/*
* If >= 4GB installed then memory from TOLUD to 4GB
@ -123,15 +123,15 @@ static void mch_domain_read_resources(struct device *dev)
*/
touud >>= 10; /* Convert to KB */
if (touud > 4096 * 1024) {
ram_resource(dev, idx++, 4096 * 1024, touud - (4096 * 1024));
ram_resource_kb(dev, idx++, 4096 * 1024, touud - (4096 * 1024));
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud >> 10) - 4096);
}
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
"size=0x%llx\n", ((u64)tomk) << 10, ((u64)uma_sizek) << 10);
/* Don't use uma_resource() as our UMA touches the PCI hole. */
fixed_mem_resource(dev, idx++, tomk, uma_sizek, IORESOURCE_RESERVE);
/* Don't use uma_resource_kb() as our UMA touches the PCI hole. */
fixed_mem_resource_kb(dev, idx++, tomk, uma_sizek, IORESOURCE_RESERVE);
mmconf_resource(dev, idx++);
}

14
src/northbridge/intel/haswell/northbridge.c
View File

@ -287,13 +287,13 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
/* 0 - > 0xa0000 */
base_k = 0;
size_k = (0xa0000 >> 10) - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* 0xc0000 -> TSEG - DPR */
base_k = 0xc0000 >> 10;
size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
size_k -= dpr.size * MiB / KiB;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* TSEG - DPR -> BGSM */
resource = new_resource(dev, index++);
@ -316,15 +316,15 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
touud_k = mc_values[TOUUD_REG] >> 10;
size_k = touud_k - base_k;
if (touud_k > base_k)
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: Legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
mmio_resource_kb(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource_kb(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
*resource_cnt = index;
}
@ -342,8 +342,8 @@ static void mc_read_resources(struct device *dev)
/* Add VT-d MMIO resources, if capable */
if (vtd_capable) {
mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB);
mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB);
mmio_resource_kb(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB);
mmio_resource_kb(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB);
}
/* Calculate and add DRAM resources */

4
src/northbridge/intel/i440bx/northbridge.c
View File

@ -61,8 +61,8 @@ static void i440bx_domain_read_resources(struct device *dev)
/* Report the memory regions. */
idx = 10;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tolmk - 768);
ram_resource_kb(dev, idx++, 0, 640);
ram_resource_kb(dev, idx++, 768, tolmk - 768);
}
}

14
src/northbridge/intel/i945/northbridge.c
View File

@ -75,15 +75,15 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk_stolen / KiB));
/* Report the memory regions */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
ram_resource(dev, idx++, 1 * MiB / KiB, (tomk - 1 * MiB / KiB));
uma_resource(dev, idx++, uma_memory_base / KiB, uma_memory_size / KiB);
mmio_resource(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB);
uma_resource(dev, idx++, cbmem_topk, delta_cbmem);
ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
ram_resource_kb(dev, idx++, 1 * MiB / KiB, (tomk - 1 * MiB / KiB));
uma_resource_kb(dev, idx++, uma_memory_base / KiB, uma_memory_size / KiB);
mmio_resource_kb(dev, idx++, tseg_memory_base / KiB, tseg_memory_size / KiB);
uma_resource_kb(dev, idx++, cbmem_topk, delta_cbmem);
/* legacy VGA memory */
mmio_resource(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
mmio_resource_kb(dev, idx++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
/* RAM to be used for option roms and BIOS */
reserved_ram_resource(dev, idx++, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, (1 * MiB - 0xc0000) / KiB);
}
static void mch_domain_set_resources(struct device *dev)

20
src/northbridge/intel/ironlake/northbridge.c
View File

@ -54,8 +54,8 @@ static void add_fixed_resources(struct device *dev, int index)
resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
mmio_resource_kb(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
reserved_ram_resource_kb(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
}
#if CONFIG(HAVE_ACPI_TABLES)
@ -105,10 +105,10 @@ static void mc_read_resources(struct device *dev)
printk(BIOS_DEBUG, "TOUUD: 0x%x\n", (unsigned int)touud);
/* Report the memory regions */
ram_resource(dev, index++, 0, 0xa0000 / KiB);
ram_resource(dev, index++, 1 * MiB / KiB, (tseg_base - 1 * MiB) / KiB);
ram_resource_kb(dev, index++, 0, 0xa0000 / KiB);
ram_resource_kb(dev, index++, 1 * MiB / KiB, (tseg_base - 1 * MiB) / KiB);
mmio_resource(dev, index++, tseg_base / KiB, CONFIG_SMM_TSEG_SIZE / KiB);
mmio_resource_kb(dev, index++, tseg_base / KiB, CONFIG_SMM_TSEG_SIZE / KiB);
reg16 = pci_read_config16(pcidev_on_root(0, 0), GGC);
const int uma_sizes_gtt[16] =
@ -130,17 +130,17 @@ static void mc_read_resources(struct device *dev)
if (gtt_base > tseg_end) {
/* Reserve the gap. MMIO doesn't work in this range. Keep
it uncacheable, though, for easier MTRR allocation. */
mmio_resource(dev, index++, tseg_end / KiB, (gtt_base - tseg_end) / KiB);
mmio_resource_kb(dev, index++, tseg_end / KiB, (gtt_base - tseg_end) / KiB);
}
mmio_resource(dev, index++, gtt_base / KiB, uma_size_gtt * KiB);
mmio_resource(dev, index++, igd_base / KiB, uma_size_igd * KiB);
mmio_resource_kb(dev, index++, gtt_base / KiB, uma_size_gtt * KiB);
mmio_resource_kb(dev, index++, igd_base / KiB, uma_size_igd * KiB);
if (touud > 4096)
ram_resource(dev, index++, (4096 * KiB), ((touud - 4096) * KiB));
ram_resource_kb(dev, index++, (4096 * KiB), ((touud - 4096) * KiB));
/* This memory is not DMA-capable. */
if (touud >= 8192 - 64)
bad_ram_resource(dev, index++, 0x1fc000000ULL / KiB, 0x004000000 / KiB);
bad_ram_resource_kb(dev, index++, 0x1fc000000ULL / KiB, 0x004000000 / KiB);
add_fixed_resources(dev, index);
}

18
src/northbridge/intel/pineview/northbridge.c
View File

@ -35,8 +35,8 @@ static void add_fixed_resources(struct device *dev, int index)
| IORESOURCE_STORED
| IORESOURCE_ASSIGNED;
mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
mmio_resource_kb(dev, index++, legacy_hole_base_k, (0xc0000 / KiB) - legacy_hole_base_k);
reserved_ram_resource_kb(dev, index++, 0xc0000 / KiB, (0x100000 - 0xc0000) / KiB);
}
static void mch_domain_read_resources(struct device *dev)
@ -98,12 +98,12 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_DEBUG, "Unused RAM between cbmem_top and TOMK: 0x%xK\n", delta_cbmem);
/* Report the memory regions */
ram_resource(dev, index++, 0, 0xa0000 / KiB);
ram_resource(dev, index++, 1 * MiB / KiB, tomk - 1 * MiB / KiB);
mmio_resource(dev, index++, tseg_basek, tseg_sizek);
mmio_resource(dev, index++, gtt_basek, gsm_sizek);
mmio_resource(dev, index++, igd_basek, gms_sizek);
reserved_ram_resource(dev, index++, cbmem_topk, delta_cbmem);
ram_resource_kb(dev, index++, 0, 0xa0000 / KiB);
ram_resource_kb(dev, index++, 1 * MiB / KiB, tomk - 1 * MiB / KiB);
mmio_resource_kb(dev, index++, tseg_basek, tseg_sizek);
mmio_resource_kb(dev, index++, gtt_basek, gsm_sizek);
mmio_resource_kb(dev, index++, igd_basek, gms_sizek);
reserved_ram_resource_kb(dev, index++, cbmem_topk, delta_cbmem);
/*
* If > 4GB installed then memory from TOLUD to 4GB
@ -111,7 +111,7 @@ static void mch_domain_read_resources(struct device *dev)
*/
touud >>= 10; /* Convert to KB */
if (touud > top32memk) {
ram_resource(dev, index++, top32memk, touud - top32memk);
ram_resource_kb(dev, index++, top32memk, touud - top32memk);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud - top32memk) / KiB);
}

22
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -64,23 +64,23 @@ static struct device_operations pci_domain_ops = {
static void add_fixed_resources(struct device *dev, int index)
{
mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
mmio_resource_kb(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
mmio_resource_kb(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10, (0x100000 - 0xc0000) >> 10);
if (is_sandybridge()) {
/* Required for SandyBridge sighting 3715511 */
bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
bad_ram_resource_kb(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10);
bad_ram_resource_kb(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10);
}
/* Reserve IOMMU BARs */
const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
if (!(capid0_a & (1 << 23))) {
mmio_resource(dev, index++, GFXVT_BASE >> 10, 4);
mmio_resource(dev, index++, VTVC0_BASE >> 10, 4);
mmio_resource_kb(dev, index++, GFXVT_BASE >> 10, 4);
mmio_resource_kb(dev, index++, VTVC0_BASE >> 10, 4);
}
}
@ -200,15 +200,15 @@ static void mc_read_resources(struct device *dev)
dpr_size_k = dpr.size * MiB / KiB;
tomk -= dpr_size_k;
dpr_base_k = (tseg_base - dpr.size * MiB) / KiB;
reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k);
reserved_ram_resource_kb(dev, index++, dpr_base_k, dpr_size_k);
printk(BIOS_DEBUG, "DPR base 0x%08x size %uM\n", dpr_base_k * KiB, dpr.size);
}
printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);
/* Report the memory regions */
ram_resource(dev, index++, 0, legacy_hole_base_k);
ram_resource(dev, index++, legacy_hole_base_k + legacy_hole_size_k,
ram_resource_kb(dev, index++, 0, legacy_hole_base_k);
ram_resource_kb(dev, index++, legacy_hole_base_k + legacy_hole_size_k,
(tomk - (legacy_hole_base_k + legacy_hole_size_k)));
/*
@ -217,7 +217,7 @@ static void mc_read_resources(struct device *dev)
*/
touud >>= 10; /* Convert to KB */
if (touud > 4096 * 1024) {
ram_resource(dev, index++, 4096 * 1024, touud - (4096 * 1024));
ram_resource_kb(dev, index++, 4096 * 1024, touud - (4096 * 1024));
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", (touud >> 10) - 4096);
}

14
src/northbridge/intel/x4x/northbridge.c
View File

@ -81,12 +81,12 @@ static void mch_domain_read_resources(struct device *dev)
printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
/* Report the memory regions */
ram_resource(dev, index++, 0, legacy_hole_base_k);
mmio_resource(dev, index++, legacy_hole_base_k,
ram_resource_kb(dev, index++, 0, legacy_hole_base_k);
mmio_resource_kb(dev, index++, legacy_hole_base_k,
(0xc0000 >> 10) - legacy_hole_base_k);
reserved_ram_resource(dev, index++, 0xc0000 >> 10,
reserved_ram_resource_kb(dev, index++, 0xc0000 >> 10,
(0x100000 - 0xc0000) >> 10);
ram_resource(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10)));
ram_resource_kb(dev, index++, 0x100000 >> 10, (tomk - (0x100000 >> 10)));
/*
* If >= 4GB installed then memory from TOLUD to 4GB
@ -94,17 +94,17 @@ static void mch_domain_read_resources(struct device *dev)
*/
touud >>= 10; /* Convert to KB */
if (touud > top32memk) {
ram_resource(dev, index++, top32memk, touud - top32memk);
ram_resource_kb(dev, index++, top32memk, touud - top32memk);
printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
(touud - top32memk) >> 10);
}
printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x size=0x%08x\n",
tomk << 10, uma_sizek << 10);
uma_resource(dev, index++, tomk, uma_sizek);
uma_resource_kb(dev, index++, tomk, uma_sizek);
/* Reserve high memory where the NB BARs are up to 4GiB */
fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10,
fixed_mem_resource_kb(dev, index++, DEFAULT_HECIBAR >> 10,
top32memk - (DEFAULT_HECIBAR >> 10),
IORESOURCE_RESERVE);

16
src/soc/amd/cezanne/root_complex.c
View File

@ -118,27 +118,27 @@ static void read_resources(struct device *dev)
pci_dev_read_resources for it */
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_resource(dev, idx++, (1 * MiB) / KiB,
ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
(early_reserved_dram_start - (1 * MiB)) / KiB);
/* DRAM reserved for early coreboot usage */
reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
reserved_ram_resource_kb(dev, idx++, early_reserved_dram_start / KiB,
(early_reserved_dram_end - early_reserved_dram_start) / KiB);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_resource(dev, idx++, early_reserved_dram_end / KiB,
ram_resource_kb(dev, idx++, early_reserved_dram_end / KiB,
(mem_usable - early_reserved_dram_end) / KiB);
mmconf_resource(dev, idx++);
@ -162,9 +162,9 @@ static void read_resources(struct device *dev)
continue; /* Done separately */
if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
else
printk(BIOS_ERR, "failed to set resources for type %d\n",
res->type);

2
src/soc/amd/cezanne/uart.c
View File

@ -87,7 +87,7 @@ static void uart_enable(struct device *dev)
static void uart_read_resources(struct device *dev)
{
mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4);
}
struct device_operations cezanne_uart_mmio_ops = {

2
src/soc/amd/common/block/i2c/i2c.c
View File

@ -117,7 +117,7 @@ void i2c_soc_init(void)
static void i2c_read_resources(struct device *dev)
{
mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4);
}
struct device_operations soc_amd_i2c_mmio_ops = {

2
src/soc/amd/common/block/lpc/lpc.c
View File

@ -117,7 +117,7 @@ static void lpc_read_resources(struct device *dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */
fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / KiB, 1,
fixed_mem_resource_kb(dev, 2, SPI_BASE_ADDRESS / KiB, 1,
IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3); /* IOAPIC */

16
src/soc/amd/picasso/root_complex.c
View File

@ -118,25 +118,25 @@ static void read_resources(struct device *dev)
pci_dev_read_resources for it */
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
/* 1MB - bottom of DRAM reserved for early coreboot usage */
ram_resource(dev, idx++, (1 * MiB) / KiB,
ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
(early_reserved_dram_start - (1 * MiB)) / KiB);
/* DRAM reserved for early coreboot usage */
reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
reserved_ram_resource_kb(dev, idx++, early_reserved_dram_start / KiB,
(early_reserved_dram_end - early_reserved_dram_start) / KiB);
/* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used. */
ram_resource(dev, idx++, early_reserved_dram_end / KiB,
ram_resource_kb(dev, idx++, early_reserved_dram_end / KiB,
(mem_usable - early_reserved_dram_end) / KiB);
mmconf_resource(dev, idx++);
@ -160,9 +160,9 @@ static void read_resources(struct device *dev)
continue; /* Done separately */
if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
else
printk(BIOS_ERR, "failed to set resources for type %d\n",
res->type);

2
src/soc/amd/picasso/uart.c
View File

@ -105,7 +105,7 @@ static void uart_enable(struct device *dev)
static void uart_read_resources(struct device *dev)
{
mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4);
}
struct device_operations picasso_uart_mmio_ops = {

16
src/soc/amd/sabrina/root_complex.c
View File

@ -120,27 +120,27 @@ static void read_resources(struct device *dev)
pci_dev_read_resources for it */
/* 0x0 - 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
/* 0xa0000 - 0xbffff: legacy VGA */
mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
/* 0xc0000 - 0xfffff: Option ROM */
reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
/* 1MiB - bottom of DRAM reserved for early coreboot usage */
ram_resource(dev, idx++, (1 * MiB) / KiB,
ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
(early_reserved_dram_start - (1 * MiB)) / KiB);
/* DRAM reserved for early coreboot usage */
reserved_ram_resource(dev, idx++, early_reserved_dram_start / KiB,
reserved_ram_resource_kb(dev, idx++, early_reserved_dram_start / KiB,
(early_reserved_dram_end - early_reserved_dram_start) / KiB);
/*
* top of DRAM consumed early - low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_resource(dev, idx++, early_reserved_dram_end / KiB,
ram_resource_kb(dev, idx++, early_reserved_dram_end / KiB,
(mem_usable - early_reserved_dram_end) / KiB);
mmconf_resource(dev, idx++);
@ -164,9 +164,9 @@ static void read_resources(struct device *dev)
continue; /* Done separately */
if (res->type == EFI_RESOURCE_SYSTEM_MEMORY)
ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
else if (res->type == EFI_RESOURCE_MEMORY_RESERVED)
reserved_ram_resource(dev, idx++, res->addr / KiB, res->length / KiB);
reserved_ram_resource_kb(dev, idx++, res->addr / KiB, res->length / KiB);
else
printk(BIOS_ERR, "Error: failed to set resources for type %d\n",
res->type);

2
src/soc/amd/sabrina/uart.c
View File

@ -114,7 +114,7 @@ static void uart_enable(struct device *dev)
static void uart_read_resources(struct device *dev)
{
mmio_resource(dev, 0, dev->path.mmio.addr / KiB, 4);
mmio_resource_kb(dev, 0, dev->path.mmio.addr / KiB, 4);
}
struct device_operations sabrina_uart_mmio_ops = {

14
src/soc/amd/stoneyridge/northbridge.c
View File

@ -396,23 +396,23 @@ void domain_read_resources(struct device *dev)
pci_domain_read_resources(dev);
/* 0x0 -> 0x9ffff */
ram_resource(dev, idx++, 0, 0xa0000 / KiB);
ram_resource_kb(dev, idx++, 0, 0xa0000 / KiB);
/* 0xa0000 -> 0xbffff: legacy VGA */
mmio_resource(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
mmio_resource_kb(dev, idx++, 0xa0000 / KiB, 0x20000 / KiB);
/* 0xc0000 -> 0xfffff: Option ROM */
reserved_ram_resource(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
reserved_ram_resource_kb(dev, idx++, 0xc0000 / KiB, 0x40000 / KiB);
/*
* 0x100000 (1MiB) -> low top usable RAM
* cbmem_top() accounts for low UMA and TSEG if they are used.
*/
ram_resource(dev, idx++, (1 * MiB) / KiB,
ram_resource_kb(dev, idx++, (1 * MiB) / KiB,
(mem_useable - (1 * MiB)) / KiB);
/* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */
reserved_ram_resource(dev, idx++, mem_useable / KiB,
reserved_ram_resource_kb(dev, idx++, mem_useable / KiB,
(tom.lo - mem_useable) / KiB);
/* If there is memory above 4GiB */
@ -424,12 +424,12 @@ void domain_read_resources(struct device *dev)
high_mem_useable = ((uint64_t)high_tom.lo |
((uint64_t)high_tom.hi << 32));
ram_resource(dev, idx++, (4ull * GiB) / KiB,
ram_resource_kb(dev, idx++, (4ull * GiB) / KiB,
((high_mem_useable - (4ull * GiB)) / KiB));
/* High top usable RAM -> high top RAM */
if (uma_base >= (4ull * GiB)) {
reserved_ram_resource(dev, idx++, uma_base / KiB,
reserved_ram_resource_kb(dev, idx++, uma_base / KiB,
uma_size / KiB);
}
}

2
src/soc/cavium/cn81xx/soc.c
View File

@ -323,7 +323,7 @@ void bootmem_platform_add_ranges(void)
static void soc_read_resources(struct device *dev)
{
// HACK: Don't advertise bootblock romstage CAR region, it's broken...
ram_resource(dev, 0, 2 * KiB, sdram_size_mb() * KiB - 2 * KiB);
ram_resource_kb(dev, 0, 2 * KiB, sdram_size_mb() * KiB - 2 * KiB);
}
static void soc_init_atf(void)

2
src/soc/intel/alderlake/pmc.c
View File

@ -85,7 +85,7 @@ static void soc_pmc_read_resources(struct device *dev)
struct resource *res;
/* Add the fixed MMIO resource */
mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
/* Add the fixed I/O resource */
res = new_resource(dev, 1);

4
src/soc/intel/apollolake/systemagent.c
View File

@ -32,13 +32,13 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
return;
if (MCHBAR32(GFXVTBAR) & VTBAR_ENABLED) {
mmio_resource(dev, *index,
mmio_resource_kb(dev, *index,
(MCHBAR64(GFXVTBAR) & VTBAR_MASK) / KiB,
VTBAR_SIZE / KiB);
(*index)++;
}
if (MCHBAR32(DEFVTBAR) & VTBAR_ENABLED) {
mmio_resource(dev, *index,
mmio_resource_kb(dev, *index,
(MCHBAR64(DEFVTBAR) & VTBAR_MASK) / KiB,
VTBAR_SIZE / KiB);
(*index)++;

2
src/soc/intel/baytrail/lpe.c
View File

@ -147,7 +147,7 @@ static void lpe_read_resources(struct device *dev)
{
pci_dev_read_resources(dev);
reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE,
reserved_ram_resource_kb(dev, FIRMWARE_PCI_REG_BASE,
FIRMWARE_PHYS_BASE >> 10,
FIRMWARE_PHYS_LENGTH >> 10);
}

16
src/soc/intel/baytrail/northcluster.c
View File

@ -77,12 +77,12 @@ static void nc_read_resources(struct device *dev)
/* PCIe memory-mapped config space access - 256 MiB. */
mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
mmio_resource_kb(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
/* 0 -> 0xa0000 */
base_k = RES_IN_KiB(0);
size_k = RES_IN_KiB(0xa0000) - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* The SMMRR registers are 1MiB granularity with smmrrh being
* inclusive of the SMM region. */
@ -92,14 +92,14 @@ static void nc_read_resources(struct device *dev)
/* 0xc0000 -> smrrl - cacheable and usable */
base_k = RES_IN_KiB(0xc0000);
size_k = smmrrl - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
if (smmrrh > smmrrl)
reserved_ram_resource(dev, index++, smmrrl, smmrrh - smmrrl);
reserved_ram_resource_kb(dev, index++, smmrrl, smmrrh - smmrrl);
/* All address space between bmbound and smmrrh is unusable. */
bmbound_k = RES_IN_KiB(nc_read_top_of_low_memory());
mmio_resource(dev, index++, smmrrh, bmbound_k - smmrrh);
mmio_resource_kb(dev, index++, smmrrh, bmbound_k - smmrrh);
/*
* The BMBOUND_HI register matches register bits of 31:24 with address
@ -108,7 +108,7 @@ static void nc_read_resources(struct device *dev)
bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
bmbound_hi = RES_IN_KiB(bmbound_hi) << 4;
if (bmbound_hi > four_gig_kib)
ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib);
ram_resource_kb(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib);
/*
* Reserve everything between A segment and 1MB:
@ -116,8 +116,8 @@ static void nc_read_resources(struct device *dev)
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
mmio_resource_kb(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource_kb(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
}
static void nc_generate_ssdt(const struct device *dev)

2
src/soc/intel/baytrail/southcluster.c
View File

@ -26,7 +26,7 @@
static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr,
unsigned long size)
{
mmio_resource(dev, i, addr >> 10, size >> 10);
mmio_resource_kb(dev, i, addr >> 10, size >> 10);
}
static void sc_add_mmio_resources(struct device *dev)

2
src/soc/intel/braswell/lpe.c
View File

@ -154,7 +154,7 @@ static void lpe_read_resources(struct device *dev)
res->align = 12;
res->flags = IORESOURCE_MEM;
reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10,
reserved_ram_resource_kb(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10,
FIRMWARE_PHYS_LENGTH >> 10);
}

18
src/soc/intel/braswell/northcluster.c
View File

@ -99,26 +99,26 @@ static void nc_read_resources(struct device *dev)
/* PCIe memory-mapped config space access - 256 MiB. */
mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1);
mmio_resource(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
mmio_resource_kb(dev, BUNIT_MMCONF_REG, RES_IN_KiB(mmconf), 256 * 1024);
/* 0 -> 0xa0000 */
base_k = RES_IN_KiB(0);
size_k = RES_IN_KiB(0xa0000) - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* High memory -> fsp_res_base - cacheable and usable */
base_k = RES_IN_KiB(0x100000);
size_k = fsp_res_base_k - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* fsp_res_base -> tseg_top - Reserved */
base_k = fsp_res_base_k;
size_k = tseg_top_k - base_k;
reserved_ram_resource(dev, index++, base_k, size_k);
reserved_ram_resource_kb(dev, index++, base_k, size_k);
/* TSEG TOP -> bmbound is memory backed mmio. */
bmbound_k = RES_IN_KiB(nc_read_top_of_low_memory());
mmio_resource(dev, index++, tseg_top_k, bmbound_k - tseg_top_k);
mmio_resource_kb(dev, index++, tseg_top_k, bmbound_k - tseg_top_k);
/*
* The BMBOUND_HI register matches register bits of 31:24 with address
@ -127,7 +127,7 @@ static void nc_read_resources(struct device *dev)
bmbound_hi = iosf_bunit_read(BUNIT_BMBOUND_HI) & ~((1 << 24) - 1);
bmbound_hi = RES_IN_KiB(bmbound_hi) << 4;
if (bmbound_hi > four_gig_kib)
ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib);
ram_resource_kb(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib);
/*
* Reserve everything between A segment and 1MB:
@ -135,15 +135,15 @@ static void nc_read_resources(struct device *dev)
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
mmio_resource_kb(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource_kb(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10);
/*
* Reserve local APIC
*/
base_k = RES_IN_KiB(LAPIC_DEFAULT_BASE);
size_k = RES_IN_KiB(0x00100000);
mmio_resource(dev, index++, base_k, size_k);
mmio_resource_kb(dev, index++, base_k, size_k);
}
static void nc_generate_ssdt(const struct device *dev)

2
src/soc/intel/braswell/southcluster.c
View File

@ -48,7 +48,7 @@ static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode)
static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr,
unsigned long size)
{
mmio_resource(dev, i, addr >> 10, size >> 10);
mmio_resource_kb(dev, i, addr >> 10, size >> 10);
}
static void sc_add_mmio_resources(struct device *dev)

14
src/soc/intel/broadwell/northbridge.c
View File

@ -317,13 +317,13 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
/* 0 - > 0xa0000 */
base_k = 0;
size_k = (0xa0000 >> 10) - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* 0xc0000 -> TSEG - DPR */
base_k = 0xc0000 >> 10;
size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k;
size_k -= dpr_size >> 10;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* TSEG - DPR -> BGSM */
resource = new_resource(dev, index++);
@ -346,15 +346,15 @@ static void mc_add_dram_resources(struct device *dev, int *resource_cnt)
touud_k = mc_values[TOUUD_REG] >> 10;
size_k = touud_k - base_k;
if (touud_k > base_k)
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* Reserve everything between A segment and 1MB:
*
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
mmio_resource_kb(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource_kb(dev, index++, (0xc0000 >> 10),
(0x100000 - 0xc0000) >> 10);
*resource_cnt = index;
@ -374,9 +374,9 @@ static void systemagent_read_resources(struct device *dev)
/* Add VT-d MMIO resources if capable */
if (vtd_capable) {
mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB,
mmio_resource_kb(dev, index++, GFXVT_BASE_ADDRESS / KiB,
GFXVT_BASE_SIZE / KiB);
mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB,
mmio_resource_kb(dev, index++, VTVC0_BASE_ADDRESS / KiB,
VTVC0_BASE_SIZE / KiB);
}

2
src/soc/intel/cannonlake/pmc.c
View File

@ -74,7 +74,7 @@ static void soc_pmc_read_resources(struct device *dev)
struct resource *res;
/* Add the fixed MMIO resource */
mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
/* Add the fixed I/O resource */
res = new_resource(dev, 1);

2
src/soc/intel/common/block/fast_spi/fast_spi.c
View File

@ -529,7 +529,7 @@ static void fast_spi_read_resources(struct device *dev)
pci_dev_read_resources(dev);
/* Add SPI flash MMIO window as a reserved resource. */
mmio_resource(dev, 0, FLASH_BASE_ADDR / KiB, FLASH_MMIO_SIZE / KiB);
mmio_resource_kb(dev, 0, FLASH_BASE_ADDR / KiB, FLASH_MMIO_SIZE / KiB);
}
static struct device_operations fast_spi_dev_ops = {

2
src/soc/intel/common/block/p2sb/ioe_p2sb.c
View File

@ -28,7 +28,7 @@ void ioe_p2sb_enable_bar(void)
static void read_resources(struct device *dev)
{
mmio_resource(dev, 0, IOE_P2SB_BAR / KiB, IOE_P2SB_SIZE / KiB);
mmio_resource_kb(dev, 0, IOE_P2SB_BAR / KiB, IOE_P2SB_SIZE / KiB);
}
struct device_operations device_ops = {

2
src/soc/intel/common/block/p2sb/p2sb.c
View File

@ -128,7 +128,7 @@ static void read_resources(struct device *dev)
* The following code makes sure that it doesn't change if the device
* is visible and the resource allocator is being run.
*/
mmio_resource(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB);
mmio_resource_kb(dev, PCI_BASE_ADDRESS_0, P2SB_BAR / KiB, P2SB_SIZE / KiB);
}
static const struct device_operations device_ops = {

18
src/soc/intel/common/block/systemagent/systemagent.c
View File

@ -108,7 +108,7 @@ void sa_add_fixed_mmio_resources(struct device *dev, int *resource_cnt,
sa_fixed_resources[i].description, sa_fixed_resources[i].base,
sa_fixed_resources[i].size);
mmio_resource(dev, index++, base / KiB, size / KiB);
mmio_resource_kb(dev, index++, base / KiB, size / KiB);
}
*resource_cnt = index;
@ -197,26 +197,26 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
/* 0 - > 0xa0000 */
base_k = 0;
size_k = (0xa0000 / KiB) - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* 0xc0000 -> top_of_ram */
base_k = 0xc0000 / KiB;
size_k = (top_of_ram / KiB) - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
sa_get_mem_map(dev, &sa_map_values[0]);
/* top_of_ram -> TOLUD */
base_k = top_of_ram;
size_k = sa_map_values[SA_TOLUD_REG] - base_k;
mmio_resource(dev, index++, base_k / KiB, size_k / KiB);
mmio_resource_kb(dev, index++, base_k / KiB, size_k / KiB);
/* 4GiB -> TOUUD */
base_k = 4 * (GiB / KiB); /* 4GiB */
touud_k = sa_map_values[SA_TOUUD_REG] / KiB;
size_k = touud_k - base_k;
if (touud_k > base_k)
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/*
* Reserve everything between A segment and 1MB:
@ -224,8 +224,8 @@ static void sa_add_dram_resources(struct device *dev, int *resource_count)
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xfffff: RAM
*/
mmio_resource(dev, index++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
reserved_ram_resource(dev, index++, 0xc0000 / KiB,
mmio_resource_kb(dev, index++, 0xa0000 / KiB, (0xc0000 - 0xa0000) / KiB);
reserved_ram_resource_kb(dev, index++, 0xc0000 / KiB,
(1*MiB - 0xc0000) / KiB);
*resource_count = index;
@ -249,7 +249,7 @@ static void imr_resource(struct device *dev, int idx, uint32_t base,
* out of MTRRs. Memory reserved by IMRs is not usable for host
* so mark it reserved.
*/
reserved_ram_resource(dev, idx, base_k, size_k);
reserved_ram_resource_kb(dev, idx, base_k, size_k);
}
/*
@ -295,7 +295,7 @@ static void systemagent_read_resources(struct device *dev)
/* Reserve the window used for extended BIOS decoding. */
if (CONFIG(FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW))
mmio_resource(dev, index++, CONFIG_EXT_BIOS_WIN_BASE / KiB,
mmio_resource_kb(dev, index++, CONFIG_EXT_BIOS_WIN_BASE / KiB,
CONFIG_EXT_BIOS_WIN_SIZE / KiB);
}

10
src/soc/intel/denverton_ns/systemagent.c
View File

@ -238,12 +238,12 @@ static void mc_add_dram_resources(struct device *dev)
/* 0 - > 0xa0000 */
base_k = 0;
size_k = (0xa0000 >> 10) - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* 0x100000 -> top_of_ram */
base_k = 0x100000 >> 10;
size_k = (top_of_ram >> 10) - base_k;
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/* top_of_ram -> TSEG */
resource = new_resource(dev, index++);
@ -269,7 +269,7 @@ static void mc_add_dram_resources(struct device *dev)
touud_k = mc_values[TOUUD_REG] >> 10;
size_k = touud_k - base_k;
if (touud_k > base_k)
ram_resource(dev, index++, base_k, size_k);
ram_resource_kb(dev, index++, base_k, size_k);
/*
* Reserve everything between A segment and 1MB:
@ -277,8 +277,8 @@ static void mc_add_dram_resources(struct device *dev)
* 0xa0000 - 0xbffff: legacy VGA
* 0xc0000 - 0xfffff: reserved RAM
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
mmio_resource_kb(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource_kb(dev, index++, (0xc0000 >> 10),
(0x100000 - 0xc0000) >> 10);
}

2
src/soc/intel/elkhartlake/pmc.c
View File

@ -71,7 +71,7 @@ static void soc_pmc_read_resources(struct device *dev)
{
struct resource *res;
mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
res = new_resource(dev, 1);
res->base = (resource_t)ACPI_BASE_ADDRESS;

2
src/soc/intel/jasperlake/pmc.c
View File

@ -71,7 +71,7 @@ static void soc_pmc_read_resources(struct device *dev)
{
struct resource *res;
mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
res = new_resource(dev, 1);
res->base = (resource_t)ACPI_BASE_ADDRESS;

12
src/soc/intel/quark/northcluster.c
View File

@ -20,7 +20,7 @@ static void nc_read_resources(struct device *dev)
/* 0 -> 0xa0000 */
base_k = 0;
size_k = 0xa0000 - base_k;
ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
ram_resource_kb(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
/*
* Reserve everything between A segment and 1MB:
@ -31,28 +31,28 @@ static void nc_read_resources(struct device *dev)
*/
base_k += size_k;
size_k = 0xc0000 - base_k;
mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
mmio_resource_kb(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
base_k += size_k;
size_k = 0x100000 - base_k;
reserved_ram_resource(dev, index++, RES_IN_KIB(base_k),
reserved_ram_resource_kb(dev, index++, RES_IN_KIB(base_k),
RES_IN_KIB(size_k));
/* 0x100000 -> cbmem_top - cacheable and usable */
base_k += size_k;
size_k = (unsigned long)cbmem_top() - base_k;
ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
ram_resource_kb(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
/* cbmem_top -> 0xc0000000 - reserved */
base_k += size_k;
size_k = 0xc0000000 - base_k;
reserved_ram_resource(dev, index++, RES_IN_KIB(base_k),
reserved_ram_resource_kb(dev, index++, RES_IN_KIB(base_k),
RES_IN_KIB(size_k));
/* 0xc0000000 -> 4GiB is mmio. */
base_k += size_k;
size_k = 0x100000000ull - base_k;
mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
mmio_resource_kb(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));
}
static struct device_operations nc_ops = {

2
src/soc/intel/tigerlake/pmc.c
View File

@ -84,7 +84,7 @@ static void soc_pmc_read_resources(struct device *dev)
struct resource *res;
/* Add the fixed MMIO resource */
mmio_resource(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
mmio_resource_kb(dev, 0, PCH_PWRM_BASE_ADDRESS / KiB, PCH_PWRM_BASE_SIZE / KiB);
/* Add the fixed I/O resource */
res = new_resource(dev, 1);

16
src/soc/intel/xeon_sp/uncore.c
View File

@ -184,19 +184,19 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
base_kb = 0;
size_kb = (0xa0000 >> 10);
LOG_MEM_RESOURCE("legacy_ram", dev, index, base_kb, size_kb);
ram_resource(dev, index++, base_kb, size_kb);
ram_resource_kb(dev, index++, base_kb, size_kb);
/* 1MB -> top_of_ram i.e., cbmem_top */
base_kb = (0x100000 >> 10);
size_kb = ((uintptr_t)cbmem_top() - 1 * MiB) >> 10;
LOG_MEM_RESOURCE("low_ram", dev, index, base_kb, size_kb);
ram_resource(dev, index++, base_kb, size_kb);
ram_resource_kb(dev, index++, base_kb, size_kb);
/* Mark TSEG/SMM region as reserved */
base_kb = (mc_values[TSEG_BASE_REG] >> 10);
size_kb = (mc_values[TSEG_LIMIT_REG] - mc_values[TSEG_BASE_REG] + 1) >> 10;
LOG_MEM_RESOURCE("mmio_tseg", dev, index, base_kb, size_kb);
reserved_ram_resource(dev, index++, base_kb, size_kb);
reserved_ram_resource_kb(dev, index++, base_kb, size_kb);
/* Reserve and set up DPR */
configure_dpr(dev);
@ -204,7 +204,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
if (dpr.size) {
uint64_t dpr_base_k = (dpr.top - dpr.size) << 10;
uint64_t dpr_size_k = dpr.size << 10;
reserved_ram_resource(dev, index++, dpr_base_k, dpr_size_k);
reserved_ram_resource_kb(dev, index++, dpr_base_k, dpr_size_k);
LOG_MEM_RESOURCE("dpr", dev, index, dpr_base_k, dpr_size_k);
}
@ -213,7 +213,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
base_kb = ((mc_values[TSEG_LIMIT_REG] + 1) >> 10);
size_kb = (mc_values[TOLM_REG] - mc_values[TSEG_LIMIT_REG]) >> 10;
LOG_MEM_RESOURCE("mmio_tolm", dev, index, base_kb, size_kb);
reserved_ram_resource(dev, index++, base_kb, size_kb);
reserved_ram_resource_kb(dev, index++, base_kb, size_kb);
}
/* 4GiB -> TOHM */
@ -221,7 +221,7 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
base_kb = (0x100000000 >> 10);
size_kb = (mc_values[TOHM_REG] - 0x100000000 + 1) >> 10;
LOG_MEM_RESOURCE("high_ram", dev, index, base_kb, size_kb);
ram_resource(dev, index++, base_kb, size_kb);
ram_resource_kb(dev, index++, base_kb, size_kb);
}
/* add MMIO CFG resource */
@ -253,12 +253,12 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
base_kb = VGA_BASE_ADDRESS >> 10;
size_kb = VGA_BASE_SIZE >> 10;
LOG_MEM_RESOURCE("legacy_mmio", dev, index, base_kb, size_kb);
mmio_resource(dev, index++, base_kb, size_kb);
mmio_resource_kb(dev, index++, base_kb, size_kb);
base_kb = (0xc0000 >> 10);
size_kb = (0x100000 - 0xc0000) >> 10;
LOG_MEM_RESOURCE("legacy_write_protect", dev, index, base_kb, size_kb);
reserved_ram_resource(dev, index++, base_kb, size_kb);
reserved_ram_resource_kb(dev, index++, base_kb, size_kb);
*res_count = index;
}

2
src/soc/mediatek/mt8173/soc.c
View File

@ -12,7 +12,7 @@ void bootmem_platform_add_ranges(void)
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
}
static void soc_init(struct device *dev)

2
src/soc/mediatek/mt8183/soc.c
View File

@ -10,7 +10,7 @@
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
}
static void soc_init(struct device *dev)

2
src/soc/mediatek/mt8186/soc.c
View File

@ -17,7 +17,7 @@ void bootmem_platform_add_ranges(void)
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
}
static void soc_init(struct device *dev)

2
src/soc/mediatek/mt8192/soc.c
View File

@ -20,7 +20,7 @@ void bootmem_platform_add_ranges(void)
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
}
static void soc_init(struct device *dev)

2
src/soc/mediatek/mt8195/soc.c
View File

@ -23,7 +23,7 @@ void bootmem_platform_add_ranges(void)
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB);
}
static void soc_init(struct device *dev)

6
src/soc/nvidia/tegra124/soc.c
View File

@ -19,15 +19,15 @@ static void soc_read_resources(struct device *dev)
u32 lcdbase = fb_base_mb();
unsigned long fb_size = FB_SIZE_MB;
ram_resource(dev, 0, (uintptr_t)_dram/KiB,
ram_resource_kb(dev, 0, (uintptr_t)_dram/KiB,
(sdram_max_addressable_mb() - fb_size)*KiB -
(uintptr_t)_dram/KiB);
mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB);
mmio_resource_kb(dev, 1, lcdbase*KiB, fb_size*KiB);
u32 sdram_end_mb = sdram_size_mb() + (uintptr_t)_dram/MiB;
if (sdram_end_mb > sdram_max_addressable_mb())
ram_resource(dev, 2, sdram_max_addressable_mb()*KiB,
ram_resource_kb(dev, 2, sdram_max_addressable_mb()*KiB,
(sdram_end_mb - sdram_max_addressable_mb())*KiB);
}

6
src/soc/nvidia/tegra210/soc.c
View File

@ -36,16 +36,16 @@ static void soc_read_resources(struct device *dev)
carveout_range(i, &begin, &size);
if (size == 0)
continue;
reserved_ram_resource(dev, index++, begin * KiB, size * KiB);
reserved_ram_resource_kb(dev, index++, begin * KiB, size * KiB);
}
memory_in_range_below_4gb(&begin, &end);
size = end - begin;
ram_resource(dev, index++, begin * KiB, size * KiB);
ram_resource_kb(dev, index++, begin * KiB, size * KiB);
memory_in_range_above_4gb(&begin, &end);
size = end - begin;
ram_resource(dev, index++, begin * KiB, size * KiB);
ram_resource_kb(dev, index++, begin * KiB, size * KiB);
}
static struct device_operations soc_ops = {

6
src/soc/qualcomm/ipq40xx/soc.c
View File

@ -33,12 +33,12 @@ static void soc_read_resources(struct device *dev)
{
ipq_mem_map_t *ipq_mem_map = ((ipq_mem_map_t *)_dram);
ram_resource(dev, 0, LINUX_REGION1_START_KB, LINUX_REGION1_SIZE_KB);
ram_resource_kb(dev, 0, LINUX_REGION1_START_KB, LINUX_REGION1_SIZE_KB);
reserved_ram_resource(dev, 1, RESERVED_START_KB, RESERVED_SIZE_KB);
reserved_ram_resource_kb(dev, 1, RESERVED_START_KB, RESERVED_SIZE_KB);
/* 0x88000000 to end, is the second region for Linux */
ram_resource(dev, 2, LINUX_REGION2_START_KB,
ram_resource_kb(dev, 2, LINUX_REGION2_START_KB,
(CONFIG_DRAM_SIZE_MB * KiB) -
LINUX_REGION1_SIZE_KB - RESERVED_SIZE_KB);
}

4
src/soc/qualcomm/ipq806x/soc.c
View File

@ -10,8 +10,8 @@
static void soc_read_resources(struct device *dev)
{
/* Reserve bottom 0x150_0000 bytes for NSS, SMEM, etc. */
reserved_ram_resource(dev, 0, (uintptr_t)_dram / KiB, RESERVED_SIZE_KB);
ram_resource(dev, 0, (uintptr_t)_dram / KiB + RESERVED_SIZE_KB,
reserved_ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, RESERVED_SIZE_KB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB + RESERVED_SIZE_KB,
(CONFIG_DRAM_SIZE_MB * KiB) - RESERVED_SIZE_KB);
}

4
src/soc/qualcomm/qcs405/soc.c
View File

@ -7,8 +7,8 @@
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, (1 * GiB) / KiB);
reserved_ram_resource(dev, 1, (uintptr_t)_dram_reserved / KiB,
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, (1 * GiB) / KiB);
reserved_ram_resource_kb(dev, 1, (uintptr_t)_dram_reserved / KiB,
REGION_SIZE(dram_reserved) / KiB);
}

8
src/soc/qualcomm/sc7180/soc.c
View File

@ -12,14 +12,14 @@ static void soc_read_resources(struct device *dev)
void *start = NULL;
void *end = NULL;
ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB,
ram_resource_kb(dev, 0, (uintptr_t)ddr_region->offset / KiB,
ddr_region->size / KiB);
reserved_ram_resource(dev, 1, (uintptr_t)_dram_aop / KiB,
reserved_ram_resource_kb(dev, 1, (uintptr_t)_dram_aop / KiB,
REGION_SIZE(dram_aop) / KiB);
reserved_ram_resource(dev, 2, (uintptr_t)_dram_soc / KiB,
reserved_ram_resource_kb(dev, 2, (uintptr_t)_dram_soc / KiB,
REGION_SIZE(dram_soc) / KiB);
if (soc_modem_carve_out(&start, &end))
reserved_ram_resource(dev, 3, (uintptr_t)start / KiB, (end - start) / KiB);
reserved_ram_resource_kb(dev, 3, (uintptr_t)start / KiB, (end - start) / KiB);
}
static void soc_init(struct device *dev)

14
src/soc/qualcomm/sc7280/soc.c
View File

@ -12,20 +12,20 @@ static void soc_read_resources(struct device *dev)
void *start = NULL;
void *end = NULL;
ram_resource(dev, 0, (uintptr_t)ddr_region->offset / KiB,
ram_resource_kb(dev, 0, (uintptr_t)ddr_region->offset / KiB,
ddr_region->size / KiB);
reserved_ram_resource(dev, 1, (uintptr_t)_dram_soc / KiB,
reserved_ram_resource_kb(dev, 1, (uintptr_t)_dram_soc / KiB,
REGION_SIZE(dram_soc) / KiB);
reserved_ram_resource(dev, 2, (uintptr_t)_dram_wlan / KiB,
reserved_ram_resource_kb(dev, 2, (uintptr_t)_dram_wlan / KiB,
REGION_SIZE(dram_wlan) / KiB);
reserved_ram_resource(dev, 3, (uintptr_t)_dram_wpss / KiB,
reserved_ram_resource_kb(dev, 3, (uintptr_t)_dram_wpss / KiB,
REGION_SIZE(dram_wpss) / KiB);
reserved_ram_resource(dev, 4, (uintptr_t)_dram_aop / KiB,
reserved_ram_resource_kb(dev, 4, (uintptr_t)_dram_aop / KiB,
REGION_SIZE(dram_aop) / KiB);
reserved_ram_resource(dev, 5, (uintptr_t)_dram_cpucp / KiB,
reserved_ram_resource_kb(dev, 5, (uintptr_t)_dram_cpucp / KiB,
REGION_SIZE(dram_cpucp) / KiB);
if (soc_modem_carve_out(&start, &end))
reserved_ram_resource(dev, 6, (uintptr_t)start / KiB, (end - start) / KiB);
reserved_ram_resource_kb(dev, 6, (uintptr_t)start / KiB, (end - start) / KiB);
}
static void soc_init(struct device *dev)

2
src/soc/rockchip/rk3288/soc.c
View File

@ -13,7 +13,7 @@
static void soc_init(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
ram_resource_kb(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
if (display_init_required())
rk_display_init(dev, (uintptr_t)_framebuffer,
REGION_SIZE(framebuffer));

2
src/soc/rockchip/rk3399/soc.c
View File

@ -21,7 +21,7 @@ void bootmem_platform_add_ranges(void)
static void soc_read_resources(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, sdram_size_mb() * KiB);
}
static void soc_init(struct device *dev)

4
src/soc/samsung/exynos5250/cpu.c
View File

@ -105,8 +105,8 @@ static void cpu_read_resources(struct device *dev)
unsigned long fb_size = FB_SIZE_KB * KiB;
u32 lcdbase = get_fb_base_kb() * KiB;
ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB);
mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));
ram_resource_kb(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB);
mmio_resource_kb(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));
}
static void cpu_init(struct device *dev)

4
src/soc/samsung/exynos5420/cpu.c
View File

@ -133,8 +133,8 @@ static void cpu_read_resources(struct device *dev)
unsigned long fb_size = FB_SIZE_KB * KiB;
u32 lcdbase = get_fb_base_kb() * KiB;
ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB);
mmio_resource(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));
ram_resource_kb(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB);
mmio_resource_kb(dev, 1, lcdbase / KiB, DIV_ROUND_UP(fb_size, KiB));
}
static void cpu_init(struct device *dev)

2
src/soc/ti/am335x/soc.c
View File

@ -6,7 +6,7 @@
static void soc_enable(struct device *dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * MiB / KiB);
ram_resource_kb(dev, 0, (uintptr_t)_dram / KiB, CONFIG_DRAM_SIZE_MB * MiB / KiB);
}
struct chip_operations soc_ti_am335x_ops = {

2
src/southbridge/amd/agesa/hudson/lpc.c
View File

@ -95,7 +95,7 @@ static void hudson_lpc_read_resources(struct device *dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */
fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
fixed_mem_resource_kb(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;

2
src/southbridge/amd/cimx/sb800/lpc.c
View File

@ -29,7 +29,7 @@ void lpc_read_resources(struct device *dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */
fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
fixed_mem_resource_kb(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3);
res->base = IO_APIC_ADDR;

2
src/southbridge/amd/pi/hudson/lpc.c
View File

@ -103,7 +103,7 @@ static void hudson_lpc_read_resources(struct device *dev)
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add a memory resource for the SPI BAR. */
fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
fixed_mem_resource_kb(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;