From 27ea93d87b9bd1321950fb3a38d09ae8943a8832 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Thu, 13 Jul 2023 07:49:26 -0600 Subject: [PATCH] soc/intel/alderlake: Move RPL-HX power limits to correct file `chipset.cb` is not used when PCH-S is selected, as is the case for RPL-HX. Fix setting power limits by putting the definitions in the correct file. Change-Id: Ia823ab82afdc76c3eb6f15cd2617b0780c84e8c4 Signed-off-by: Tim Crawford --- src/soc/intel/alderlake/chipset.cb | 30 ------------------------ src/soc/intel/alderlake/chipset_pch_s.cb | 30 ++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 30 deletions(-) diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 8a7fa843dc..5dfb47de35 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -90,36 +90,6 @@ chip soc/intel/alderlake .tdp_pl4 = 114, }" - register "power_limits_config[RPL_HX_8_16_55W_CORE]" = "{ - .tdp_pl1_override = 55, - .tdp_pl2_override = 130, - .tdp_pl4 = 200, - }" - - register "power_limits_config[RPL_HX_8_12_55W_CORE]" = "{ - .tdp_pl1_override = 55, - .tdp_pl2_override = 130, - .tdp_pl4 = 200, - }" - - register "power_limits_config[RPL_HX_8_8_55W_CORE]" = "{ - .tdp_pl1_override = 55, - .tdp_pl2_override = 130, - .tdp_pl4 = 200, - }" - - register "power_limits_config[RPL_HX_6_8_55W_CORE]" = "{ - .tdp_pl1_override = 55, - .tdp_pl2_override = 130, - .tdp_pl4 = 200, - }" - - register "power_limits_config[RPL_HX_6_4_55W_CORE]" = "{ - .tdp_pl1_override = 55, - .tdp_pl2_override = 130, - .tdp_pl4 = 200, - }" - # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index 077cdb6649..2677229d57 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -92,6 +92,36 @@ chip soc/intel/alderlake .tdp_pl4 = 44, }" + register "power_limits_config[RPL_HX_8_16_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 130, + .tdp_pl4 = 200, + }" + + register "power_limits_config[RPL_HX_8_12_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 130, + .tdp_pl4 = 200, + }" + + register "power_limits_config[RPL_HX_8_8_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 130, + .tdp_pl4 = 200, + }" + + register "power_limits_config[RPL_HX_6_8_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 130, + .tdp_pl4 = 200, + }" + + register "power_limits_config[RPL_HX_6_4_55W_CORE]" = "{ + .tdp_pl1_override = 55, + .tdp_pl2_override = 130, + .tdp_pl4 = 200, + }" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file.