diff --git a/src/mainboard/system76/Kconfig b/src/mainboard/system76/Kconfig new file mode 100644 index 0000000000..62034a4222 --- /dev/null +++ b/src/mainboard/system76/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_SYSTEM76 + +choice + prompt "Mainboard model" + +source "src/mainboard/system76/*/Kconfig.name" + +endchoice + +source "src/mainboard/system76/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "System76" + +endif diff --git a/src/mainboard/system76/Kconfig.name b/src/mainboard/system76/Kconfig.name new file mode 100644 index 0000000000..7155721bee --- /dev/null +++ b/src/mainboard/system76/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_SYSTEM76 + bool "System76" diff --git a/src/mainboard/system76/kbl-u/Kconfig b/src/mainboard/system76/kbl-u/Kconfig new file mode 100644 index 0000000000..4c745e3762 --- /dev/null +++ b/src/mainboard/system76/kbl-u/Kconfig @@ -0,0 +1,104 @@ +if BOARD_SYSTEM76_GALP2 || BOARD_SYSTEM76_GALP3 || BOARD_SYSTEM76_GALP3_B + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_8192 + select EC_ACPI + select EXCLUDE_EMMC_INTERFACE + select FSP_USE_REPO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_FSP2_0 + select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_KABYLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select USE_BLOBS + select USE_OPTION_TABLE + +config MAINBOARD_DIR + string + default system76/kbl-u + +config VARIANT_DIR + string + default "galp2" if BOARD_SYSTEM76_GALP2 + default "galp3" if BOARD_SYSTEM76_GALP3 + default "galp3-b" if BOARD_SYSTEM76_GALP3_B + +config MAINBOARD_PART_NUMBER + string + default "galp2" if BOARD_SYSTEM76_GALP2 + default "galp3" if BOARD_SYSTEM76_GALP3 + default "galp3-b" if BOARD_SYSTEM76_GALP3_B + +config CBFS_SIZE + hex + default 0x600000 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1558 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1303 if BOARD_SYSTEM76_GALP2 + default 0x1313 if BOARD_SYSTEM76_GALP3 + default 0x1413 if BOARD_SYSTEM76_GALP3_B + +config CONSOLE_POST + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +# This causes UEFI to hang +#config UART_FOR_CONSOLE +# int +# default 2 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_FILE + string + default "pci8086,5916.rom" if BOARD_SYSTEM76_GALP2 + default "pci8086,5917.rom" if BOARD_SYSTEM76_GALP3 || BOARD_SYSTEM76_GALP3_B + +config VGA_BIOS_ID + string + default "8086,5916" if BOARD_SYSTEM76_GALP2 + default "8086,5917" if BOARD_SYSTEM76_GALP3 || BOARD_SYSTEM76_GALP3_B + +config PXE_ROM_ID + string + default "10ec,8168" + +config FSP_M_XIP + bool + default y + +config POST_DEVICE + bool + default n + +endif diff --git a/src/mainboard/system76/kbl-u/Kconfig.name b/src/mainboard/system76/kbl-u/Kconfig.name new file mode 100644 index 0000000000..143ac15789 --- /dev/null +++ b/src/mainboard/system76/kbl-u/Kconfig.name @@ -0,0 +1,8 @@ +config BOARD_SYSTEM76_GALP2 + bool "galp2" + +config BOARD_SYSTEM76_GALP3 + bool "galp3" + +config BOARD_SYSTEM76_GALP3_B + bool "galp3-b" diff --git a/src/mainboard/system76/kbl-u/Makefile.inc b/src/mainboard/system76/kbl-u/Makefile.inc new file mode 100644 index 0000000000..5ffe936e09 --- /dev/null +++ b/src/mainboard/system76/kbl-u/Makefile.inc @@ -0,0 +1,2 @@ +romstage-y += pei_data.c +ramstage-y += ramstage.c pei_data.c variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/kbl-u/acpi/ac.asl b/src/mainboard/system76/kbl-u/acpi/ac.asl new file mode 100644 index 0000000000..7a55e45ca3 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/ac.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (AC) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Return (ACFG) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/battery.asl b/src/mainboard/system76/kbl-u/acpi/battery.asl new file mode 100644 index 0000000000..bfda8a00cd --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/battery.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (BFCC, Zero) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0x39D0, + Zero, + Zero, + 0x40, + 0x40, + "BAT", + "0001", + "LION", + "Notebook" + }) + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = " " + PBIF [0x0A] = " " + PBIF [0x0B] = " " + PBIF [0x0C] = " " + BFCC = Zero + } + + Method (UPBI, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF) + PBIF [One] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF) + PBIF [0x02] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF) + PBIF [0x04] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF) + PBIF [0x05] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF) + PBIF [0x06] = Local0 + PBIF [0x09] = "BAT" + PBIF [0x0A] = "0001" + PBIF [0x0B] = "LION" + PBIF [0x0C] = "Notebook" + } + Else + { + IVBI () + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBI () + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x3D90 + }) + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } + + Method (UPBS, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = Zero + Local1 = Zero + If (^^AC.ACFG) + { + If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02)) + { + Local0 |= 0x02 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + } + Else + { + Local0 |= One + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + + Local7 = (Local1 & 0x8000) + If ((Local7 == 0x8000)) + { + Local1 ^= 0xFFFF + } + + Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF) + Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF) + PBST [Zero] = Local0 + PBST [One] = Local1 + PBST [0x02] = Local2 + PBST [0x03] = Local3 + If ((BFCC != ^^PCI0.LPCB.EC0.BFC0)) + { + Notify (BAT0, 0x81) // Information Change + } + } + Else + { + IVBS () + } + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBS () + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/buttons.asl b/src/mainboard/system76/kbl-u/acpi/buttons.asl new file mode 100644 index 0000000000..c86e5201a8 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/buttons.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 }) +} + +Device (SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 }) +} diff --git a/src/mainboard/system76/kbl-u/acpi/ec.asl b/src/mainboard/system76/kbl-u/acpi/ec.asl new file mode 100644 index 0000000000..11a9cda57e --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/ec.asl @@ -0,0 +1,204 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + + #include "acpi/ec_ram.asl" + + Name (ECOK, Zero) + Method (_REG, 2, Serialized) // _REG: Region Availability + { + Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) + If (((Arg0 == 0x03) && (Arg1 == One))) { + // Enable software touchpad lock and airplane mode keys + ECOS = 2 + + // Enable software backlight keys + WINF = 1 + + // Set current AC state + ^^^^AC.ACFG = ADP + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + PNOT () + + // EC is now available + ECOK = Arg1 + } + } + + Method (PTS, 1, Serialized) { + Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) + If (ECOK) { + WFNO = Zero + } + } + + Method (WAK, 1, Serialized) { + Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + If (ECOK) { + // Set current AC state + ^^^^AC.ACFG = ADP + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + Notify(^^^^AC, Zero) + Notify(^^^^BAT0, Zero) + } + } + + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle + { + Debug = "EC: Touchpad Toggle" + } + + Method (_Q0B, 0, NotSerialized) // Screen Toggle + { + Debug = "EC: Screen Toggle" + } + + Method (_Q0C, 0, NotSerialized) // Mute + { + Debug = "EC: Mute" + } + + Method (_Q0D, 0, NotSerialized) // Keyboard Backlight + { + Debug = "EC: Keyboard Backlight" + } + + Method (_Q0E, 0, NotSerialized) // Volume Down + { + Debug = "EC: Volume Down" + } + + Method (_Q0F, 0, NotSerialized) // Volume Up + { + Debug = "EC: Volume Up" + } + + Method (_Q10, 0, NotSerialized) // Switch Video Mode + { + Debug = "EC: Switch Video Mode" + } + + Method (_Q11, 0, NotSerialized) // Brightness Down + { + Debug = "EC: Brightness Down" + ^^^^HIDD.HPEM (20) + } + + Method (_Q12, 0, NotSerialized) // Brightness Up + { + Debug = "EC: Brightness Up" + ^^^^HIDD.HPEM (19) + } + + Method (_Q13, 0, NotSerialized) // Camera Toggle + { + Debug = "EC: Camera Toggle" + } + + Method (_Q14, 0, NotSerialized) // Airplane Mode + { + Debug = "EC: Airplane Mode" + ^^^^HIDD.HPEM (8) + } + + Method (_Q15, 0, NotSerialized) // Suspend Button + { + Debug = "EC: Suspend Button" + Notify (SLPB, 0x80) + } + + Method (_Q16, 0, NotSerialized) // AC Detect + { + Debug = "EC: AC Detect" + ^^^^AC.ACFG = ADP + Notify (AC, 0x80) // Status Change + Sleep (0x01F4) + If (BAT0) + { + Notify (^^^^BAT0, 0x81) // Information Change + Sleep (0x32) + Notify (^^^^BAT0, 0x80) // Status Change + Sleep (0x32) + } + } + + Method (_Q17, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (17)" + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q19, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (19)" + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q1B, 0, NotSerialized) // Lid Close + { + Debug = "EC: Lid Close" + Notify (LID0, 0x80) + } + + Method (_Q1C, 0, NotSerialized) // Thermal Trip + { + Debug = "EC: Thermal Trip" + /* TODO + Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change + Notify (\_TZ.TZ0, 0x80) // Thermal Status Change + */ + } + + Method (_Q1D, 0, NotSerialized) // Power Button + { + Debug = "EC: Power Button" + Notify (PWRB, 0x80) + } + + Method (_Q50, 0, NotSerialized) // Other Events + { + Local0 = OEM4 + If (Local0 == 0x8A) { + Debug = "EC: White Keyboard Backlight" + Notify (^^^^S76D, 0x80) + } Else { + Debug = Concatenate("EC: Other: ", ToHexString(Local0)) + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/ec_ram.asl b/src/mainboard/system76/kbl-u/acpi/ec_ram.asl new file mode 100644 index 0000000000..8820fd0d34 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/ec_ram.asl @@ -0,0 +1,185 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) +Field (ERAM, ByteAcc, Lock, Preserve) +{ + NMSG, 8, + SLED, 4, + Offset (0x02), + MODE, 1, + FAN0, 1, + TME0, 1, + TME1, 1, + FAN1, 1, + , 2, + Offset (0x03), + LSTE, 1, + LSW0, 1, + LWKE, 1, + WAKF, 1, + , 2, + PWKE, 1, + MWKE, 1, + AC0, 8, + PSV, 8, + CRT, 8, + TMP, 8, + AC1, 8, + BBST, 8, + Offset (0x0B), + Offset (0x0C), + Offset (0x0D), + Offset (0x0E), + SLPT, 8, + SWEJ, 1, + SWCH, 1, + Offset (0x10), + ADP, 1, + AFLT, 1, + BAT0, 1, + BAT1, 1, + , 3, + PWOF, 1, + WFNO, 8, + BPU0, 32, + BDC0, 32, + BFC0, 32, + BTC0, 32, + BDV0, 32, + BST0, 32, + BPR0, 32, + BRC0, 32, + BPV0, 32, + BTP0, 16, + BRS0, 16, + BCW0, 32, + BCL0, 32, + BCG0, 32, + BG20, 32, + BMO0, 64, + BIF0, 64, + BSN0, 32, + BTY0, 64, + Offset (0x67), + Offset (0x68), + ECOS, 8, + LNXD, 8, + ECPS, 8, + Offset (0x6C), + BTMP, 16, + EVTN, 8, + Offset (0x72), + PRCL, 8, + PRC0, 8, + PRC1, 8, + PRCM, 8, + PRIN, 8, + PSTE, 8, + PCAD, 8, + PEWL, 8, + PWRL, 8, + PECD, 8, + PEHI, 8, + PECI, 8, + PEPL, 8, + PEPM, 8, + PWFC, 8, + PECC, 8, + PDT0, 8, + PDT1, 8, + PDT2, 8, + PDT3, 8, + PRFC, 8, + PRS0, 8, + PRS1, 8, + PRS2, 8, + PRS3, 8, + PRS4, 8, + PRCS, 8, + PEC0, 8, + PEC1, 8, + PEC2, 8, + PEC3, 8, + CMDR, 8, + CVRT, 8, + GTVR, 8, + FANT, 8, + SKNT, 8, + AMBT, 8, + MCRT, 8, + DIM0, 8, + DIM1, 8, + PMAX, 8, + PPDT, 8, + PECH, 8, + PMDT, 8, + TSD0, 8, + TSD1, 8, + TSD2, 8, + TSD3, 8, + CPUP, 16, + MCHP, 16, + SYSP, 16, + CPAP, 16, + MCAP, 16, + SYAP, 16, + CFSP, 16, + CPUE, 16, + Offset (0xC6), + Offset (0xC7), + VGAT, 8, + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, + Offset (0xCE), + DUT1, 8, + DUT2, 8, + RPM1, 16, + RPM2, 16, + RPM4, 16, + Offset (0xD7), + DTHL, 8, + DTBP, 8, + AIRP, 8, + WINF, 8, + RINF, 8, + Offset (0xDD), + INF2, 8, + MUTE, 1, + Offset (0xE0), + RPM3, 16, + ECKS, 8, + Offset (0xE4), + , 4, + XTUF, 1, + EP12, 1, + Offset (0xE5), + INF3, 8, + Offset (0xE7), + GFOF, 8, + Offset (0xF0), + PL1T, 16, + PL2T, 16, + TAUT, 8, + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8 +} diff --git a/src/mainboard/system76/kbl-u/acpi/gpe.asl b/src/mainboard/system76/kbl-u/acpi/gpe.asl new file mode 100644 index 0000000000..13a7927189 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/gpe.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// GPP_C19 SCI +Method (_L13, 0, Serialized) { + Debug = Concatenate("GPE _L13: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == One) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/hid.asl b/src/mainboard/system76/kbl-u/acpi/hid.asl new file mode 100644 index 0000000000..c75fefa6a0 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/hid.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, Zero) + Name (HIDX, Zero) + Name (HRDY, Zero) + + Method (HDEM, 0, Serialized) + { + HBSY = Zero + Return (HIDX) + } + + Method (HDMM, 0, Serialized) + { + Return (Zero) + } + + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + HBSY = One + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = Zero + While (((Local0 < 0xFA) && HBSY)) + { + Sleep (0x04) + Local0++ + } + + If ((HBSY == One)) + { + HBSY = Zero + HIDX = Zero + Return (One) + } + Else + { + Return (Zero) + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/lid.asl b/src/mainboard/system76/kbl-u/acpi/lid.asl new file mode 100644 index 0000000000..47e9bac8f6 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/lid.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { 0x13 /* GPP_C19 */, 3 }) + + Method (_LID, 0, NotSerialized) { + DEBUG = "LID: _LID" + If (^^PCI0.LPCB.EC0.ECOK) { + Return (^^PCI0.LPCB.EC0.LSTE) + } Else { + Return (One) + } + } + + Method (_PSW, 1, NotSerialized) { + DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0)) + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.LWKE = Arg0 + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/mainboard.asl b/src/mainboard/system76/kbl-u/acpi/mainboard.asl new file mode 100644 index 0000000000..caf6688d6d --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/mainboard.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) { + #include "ac.asl" + #include "battery.asl" + #include "buttons.asl" + #include "hid.asl" + #include "lid.asl" + #include "s76.asl" +} + +Scope (_GPE) { + #include "gpe.asl" +} diff --git a/src/mainboard/system76/kbl-u/acpi/s76.asl b/src/mainboard/system76/kbl-u/acpi/s76.asl new file mode 100644 index 0000000000..f0250b5035 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/s76.asl @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Notifications: +// 0x80 - hardware backlight toggle +// 0x81 - backlight toggle +// 0x82 - backlight down +// 0x83 - backlight up +// 0x84 - backlight color change +Device (S76D) { + Name (_HID, "17761776") + Name (_UID, 0) + + // Get Airplane LED + Method (GAPL, 0, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (^^PCI0.LPCB.EC0.AIRP & 0x40) { + Return (1) + } + } + Return (0) + } + + // Set Airplane LED + Method (SAPL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0) { + ^^PCI0.LPCB.EC0.AIRP |= 0x40 + } Else { + ^^PCI0.LPCB.EC0.AIRP &= 0xBF + } + } + } + + // Get KB LED + Method (GKBL, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = One + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + ^^PCI0.LPCB.EC0.FCMD = Zero + } + Return (Local0) + } + + // Set KB Led + Method (SKBL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = Zero + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } +} diff --git a/src/mainboard/system76/kbl-u/acpi/superio.asl b/src/mainboard/system76/kbl-u/acpi/superio.asl new file mode 100644 index 0000000000..9e01ed8b92 --- /dev/null +++ b/src/mainboard/system76/kbl-u/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include diff --git a/src/mainboard/system76/kbl-u/acpi_tables.c b/src/mainboard/system76/kbl-u/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/system76/kbl-u/board_info.txt b/src/mainboard/system76/kbl-u/board_info.txt new file mode 100644 index 0000000000..56e98a39e3 --- /dev/null +++ b/src/mainboard/system76/kbl-u/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: kbl-u +Category: laptop +Release year: 2018 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/kbl-u/cmos.default b/src/mainboard/system76/kbl-u/cmos.default new file mode 100644 index 0000000000..b4890abf8d --- /dev/null +++ b/src/mainboard/system76/kbl-u/cmos.default @@ -0,0 +1 @@ +DisplayPort_Output=Mini_DisplayPort diff --git a/src/mainboard/system76/kbl-u/cmos.layout b/src/mainboard/system76/kbl-u/cmos.layout new file mode 100644 index 0000000000..f69185a1f0 --- /dev/null +++ b/src/mainboard/system76/kbl-u/cmos.layout @@ -0,0 +1,33 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 System76 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +#start length type id name +0 384 r 0 reserved_memory +384 1 e 1 DisplayPort_Output +984 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Mini_DisplayPort +1 1 USB-C + +checksums + +#checksum start end location +checksum 384 983 984 diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb new file mode 100644 index 0000000000..9c8baa9bfb --- /dev/null +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -0,0 +1,250 @@ +chip soc/intel/skylake + + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN" + + register "eist_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "gpe0_dw0" = "GPP_C" + register "gpe0_dw1" = "GPP_D" + register "gpe0_dw2" = "GPP_E" + + register "gen1_dec" = "0x000c0681" + register "gen2_dec" = "0x000c1641" + register "gen3_dec" = "0x000c0081" + register "gen4_dec" = "0x00040069" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Disable DPTF + register "dptf_enable" = "0" + + # FSP Configuration + register "ProbelessTrace" = "0" + register "EnableLan" = "0" + register "EnableSata" = "1" + register "SataSalpSupport" = "0" + register "SataMode" = "0" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "1" + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataSpeedLimit" = "2" + register "EnableAzalia" = "1" + register "DspEnable" = "0" + register "IoBufferOwnership" = "0" + register "EnableTraceHub" = "0" + register "SsicPortEnable" = "0" + register "SmbusEnable" = "1" + register "Cio2Enable" = "0" + register "ScsEmmcEnabled" = "0" + register "ScsEmmcHs400Enabled" = "0" + register "ScsSdCardEnabled" = "0" + register "PttSwitch" = "0" + register "SkipExtGfxScan" = "1" + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "SaGv" = "3" + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "PmConfigSlpS3MinAssert" = "2" # 50ms + register "PmConfigSlpS4MinAssert" = "1" # 1s + register "PmConfigSlpSusMinAssert" = "3" # 500ms + register "PmConfigSlpAMinAssert" = "3" # 2s + register "PmTimerDisabled" = "0" + + register "pirqa_routing" = "PCH_IRQ11" + register "pirqb_routing" = "PCH_IRQ10" + register "pirqc_routing" = "PCH_IRQ11" + register "pirqd_routing" = "PCH_IRQ11" + register "pirqe_routing" = "PCH_IRQ11" + register "pirqf_routing" = "PCH_IRQ11" + register "pirqg_routing" = "PCH_IRQ11" + register "pirqh_routing" = "PCH_IRQ11" + + # Root port #1 x4 (TBT) + register "PcieRpEnable[0]" = "1" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqNumber[0]" = "4" + register "PcieRpClkSrcNumber[0]" = "4" + register "PcieRpAdvancedErrorReporting[0]" = "1" + register "PcieRpLtrEnable[0]" = "1" + register "PcieRpHotPlug[0]" = "1" + + # Root port #5 x1 (LAN) + register "PcieRpEnable[4]" = "1" + register "PcieRpClkReqSupport[4]" = "1" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpAdvancedErrorReporting[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + + # Root port #6 x1 (WLAN) + register "PcieRpEnable[5]" = "1" + register "PcieRpClkReqSupport[5]" = "1" + register "PcieRpClkReqNumber[5]" = "2" + register "PcieRpClkSrcNumber[5]" = "2" + register "PcieRpAdvancedErrorReporting[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + + # Root port #9 x4 (NVMe) + register "PcieRpEnable[8]" = "1" + register "PcieRpClkReqSupport[8]" = "1" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpAdvancedErrorReporting[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + + # Configure USB2 ports + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right + register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera + register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left + register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_EMPTY" # NC + + # Configure USB3 ports + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left + + # PL2 override 44W + register "tdp_pl2_override" = "40" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + + # VR Settings Configuration for 4 Domains + #+----------------+-----------+-----------+-------------+----------+ + #| Domain/Setting | SA | IA | GT Unsliced | GT | + #+----------------+-----------+-----------+-------------+----------+ + #| Psi1Threshold | 20A | 20A | 20A | 20A | + #| Psi2Threshold | 4A | 5A | 5A | 5A | + #| Psi3Threshold | 1A | 1A | 1A | 1A | + #| Psi3Enable | 1 | 1 | 1 | 1 | + #| Psi4Enable | 1 | 1 | 1 | 1 | + #| ImonSlope | 0 | 0 | 0 | 0 | + #| ImonOffset | 0 | 0 | 0 | 0 | + #| IccMax | 5A | 64A | 31A | 31A | + #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | + #+----------------+-----------+-----------+-------------+----------+ + register "domain_vr_config[VR_SYSTEM_AGENT]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(4), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(5), + .voltage_limit = 1520, + .ac_loadline = 1030, + .dc_loadline = 1030, + }" + + register "domain_vr_config[VR_IA_CORE]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(64), + .voltage_limit = 1520, + .ac_loadline = 240, + .dc_loadline = 240, + }" + + register "domain_vr_config[VR_GT_UNSLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + register "domain_vr_config[VR_GT_SLICED]" = "{ + .vr_config_enable = 1, + .psi1threshold = VR_CFG_AMP(20), + .psi2threshold = VR_CFG_AMP(5), + .psi3threshold = VR_CFG_AMP(1), + .psi3enable = 0, + .psi4enable = 0, + .imon_slope = 0x0, + .imon_offset = 0x0, + .icc_max = VR_CFG_AMP(31), + .voltage_limit = 1520, + .ac_loadline = 310, + .dc_loadline = 310, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 16.0 off end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 on end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1f.0 on + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 off end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/system76/kbl-u/dsdt.asl b/src/mainboard/system76/kbl-u/dsdt.asl new file mode 100644 index 0000000000..2c7f2ddf7d --- /dev/null +++ b/src/mainboard/system76/kbl-u/dsdt.asl @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include + + // global NVS and variables + #include + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + // Chipset specific sleep states + #include + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/kbl-u/gpio.h b/src/mainboard/system76/kbl-u/gpio.h new file mode 100644 index 0000000000..54f599290e --- /dev/null +++ b/src/mainboard/system76/kbl-u/gpio.h @@ -0,0 +1,455 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +// Pad configuration in ramstage +static const struct pad_config gpio_table[] = { +// GPD + // System Power Management + // PM_BATLOW# + PAD_CFG_NC(GPD0), + // AC_PRESENT + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + // LAN_WAKEUP# + _PAD_CFG_STRUCT(GPD2, 0x880500, 0x0), + // PWR_BTN# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + // SUSB#_PCH + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + // SUSC#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + // SLP_A# + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPD7), + // SUSCLK + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + // PCH_SLP_WLAN# + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + // SLP_S5# + PAD_CFG_NC(GPD10), + // PCH_GPD11 + PAD_CFG_NC(GPD11), + +// GPP_A + // LPC + // TODO - SB_KBCRST# + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + // LPC_AD0 + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + // LPC_AD1 + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + // LPC_AD2 + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + // LPC_AD3 + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + // LPC_FRAME# + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + // SERIRQ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + // PCIE/USB3/SATA + // G_INT1 + PAD_CFG_NC(GPP_A7), + + // LPC + // PM_CLKRUN# + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + // PCLK_KBC + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + // PCLK_TPM + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), + + // System Power Management + // TODO - LAN_WAKEUP# + PAD_CFG_NC(GPP_A11), + + // ISH + // PCH_GPP_A12 + PAD_CFG_NC(GPP_A12), + + // System Power Management + // SUSWARN# + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + + // LPC + // S4_STATE# + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + + // System Power Management + // SUSACK# + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + + // SDIO/SDXC + // NC + PAD_CFG_NC(GPP_A16), + // NC + PAD_CFG_NC(GPP_A17), + + // ISH + // TBTA_ACE_GPIO3 + PAD_CFG_GPO(GPP_A18, 1, DEEP), + // SATA_PWR_EN + PAD_CFG_GPO(GPP_A19, 1, DEEP), + // TBTA_ACE_GPIO0 + PAD_CFG_GPO(GPP_A20, 0, DEEP), + // TBT_FRC_PWR + PAD_CFG_GPO(GPP_A21, 0, DEEP), + // PS8338B_SW + PAD_CFG_GPO(GPP_A22, 0, DEEP), + // PS8338B_PCH + PAD_CFG_GPO(GPP_A23, 0, DEEP), + +// GPP_B + // CPU Power + // CORE_VID0 + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + // CORE_VID1 + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + // System Power Management + // VRALERT# + PAD_CFG_NC(GPP_B2), + + // CPU Misc + // NC + PAD_CFG_NC(GPP_B3), + // NC + PAD_CFG_NC(GPP_B4), + + // Clock Signals + // PCIECLKRQ0# + PAD_CFG_NC(GPP_B5), + // PCIECLKRQ1# + PAD_CFG_NC(GPP_B6), + // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + // LAN_CLKREQ# + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + // TBT_CLKREQ# + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + // SSD_CLKREQ# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + + // System Power Management + // NC + PAD_CFG_NC(GPP_B11), + // SLP_S0# + PAD_CFG_NC(GPP_B12), + // PLTRST# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + // Audio - SPKR + // PCH_SPKR + PAD_CFG_NF(GPP_B14, DN_20K, DEEP, NF1), + + // LPSS + // PCH_GPP_B15 + PAD_CFG_NC(GPP_B15), + // PCH_GPP_B16 + PAD_CFG_NC(GPP_B16), + // PCH_GPP_B17 + PAD_CFG_NC(GPP_B17), + // GSPI0_BBS0 - No Reboot strap + PAD_CFG_NC(GPP_B18), + // PCH_GPP_B19 + PAD_CFG_NC(GPP_B19), + // PCH_GPP_B20 + PAD_CFG_NC(GPP_B20), + // PCH_GPP_B21 + PAD_CFG_NC(GPP_B21), + // PCH_GPP_B22 - Boot BIOS strap + PAD_CFG_NC(GPP_B22), + + // SMBUS + // PCH_GPP_B23 + PAD_CFG_NC(GPP_B23), + +// GPP_C + // SMBUS + // SMB_CLK + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + // SMB_DATA + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + // PCH_GPP_C2 + PAD_CFG_NC(GPP_C2), + // SML0CLK + PAD_CFG_NC(GPP_C3), + // SML0DATA + PAD_CFG_NC(GPP_C4), + // PCH_GPP_C5 + PAD_CFG_NC(GPP_C5), + // SML1CLK + PAD_CFG_NC(GPP_C6), + // SML1DATA + PAD_CFG_NC(GPP_C7), + + // LPSS + // NC + PAD_CFG_NC(GPP_C8), + // NC + PAD_CFG_NC(GPP_C9), + // NC + PAD_CFG_NC(GPP_C10), + // NC + PAD_CFG_NC(GPP_C11), + + // ISH + // TBTA_ACE_GPIO2 + PAD_CFG_NC(GPP_C12), + // TBCIO_PLUG_EVENT + _PAD_CFG_STRUCT(GPP_C13, 0x82880100, 0x0), + // TBTA_MRESET + PAD_CFG_NC(GPP_C14), + // TBTA_ACE_GPIO7 + PAD_CFG_NC(GPP_C15), + + // LPSS + // T_SDA + PAD_CFG_NC(GPP_C16), + // T_SCL + PAD_CFG_NC(GPP_C17), + // NC + PAD_CFG_NC(GPP_C18), + // SWI# + _PAD_CFG_STRUCT(GPP_C19, 0x40880100, 0x0), + // UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + // UEART2_RTS_N + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + // UART2_CTS_N + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + +// GPP_D + // SPI - Touch + // NC + PAD_CFG_NC(GPP_D0), + // NC + PAD_CFG_NC(GPP_D1), + // NC + PAD_CFG_NC(GPP_D2), + // NC + PAD_CFG_NC(GPP_D3), + + // NC + PAD_CFG_NC(GPP_D4), + + // ISH + // NC + PAD_CFG_NC(GPP_D5), + // NC + PAD_CFG_NC(GPP_D6), + // NC + PAD_CFG_NC(GPP_D7), + // SB_BLON + PAD_CFG_GPO(GPP_D8, 1, DEEP), + // T_INT + PAD_CFG_NC(GPP_D9), + // EDP_DET + PAD_CFG_NC(GPP_D10), + // NC + PAD_CFG_NC(GPP_D11), + // NC + PAD_CFG_NC(GPP_D12), + // NC + PAD_CFG_NC(GPP_D13), + // NC + PAD_CFG_NC(GPP_D14), + // NC + PAD_CFG_NC(GPP_D15), + // NC + PAD_CFG_NC(GPP_D16), + + // Audio - DMIC + // NC + PAD_CFG_NC(GPP_D17), + // NC + PAD_CFG_NC(GPP_D18), + // NC + PAD_CFG_NC(GPP_D19), + // NC + PAD_CFG_NC(GPP_D20), + + // SPI - Touch + // TPM_DET# + PAD_CFG_NC(GPP_D21), + // NC + PAD_CFG_NC(GPP_D22), + + // Audio - I2S + // NC + PAD_CFG_NC(GPP_D23), + +// GPP_E + // SATAXPCIE + // PCH_GPP_E0 + PAD_CFG_NC(GPP_E0), + // SATA_ODD_PRSNT# + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), + // SATAGP2 + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), + + // CPU Misc + // NC + PAD_CFG_NC(GPP_E3), + + // DEVSLP + // DEVSLP0 + PAD_CFG_NC(GPP_E4), + // DEVSLP1 + PAD_CFG_NC(GPP_E5), + // DEVSLP2 + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), + + // CPU Misc + // NC + PAD_CFG_NC(GPP_E7), + + // USB2 + // PCH_SATA_LED# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + // USB_OC#12 + PAD_CFG_NC(GPP_E9), + // USB_OC#34 + PAD_CFG_NC(GPP_E10), + // USB_OC#56 + PAD_CFG_NC(GPP_E11), + // USB_OC#78 + PAD_CFG_NC(GPP_E12), + + // Display Sidebands + // MUX_HPD + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + // HDMI_HPD + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + // SMI# + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), + // SCI# + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), + // EDP_HPD + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + // MDP_CTRLCLK + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + // MDP_CTRLDATA + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1), + // HDMI_CTRLCLK + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + // HDMI_CTRLDATA + PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_E22), + // NC + PAD_CFG_NC(GPP_E23), + +// GPP_F + // Audio - I2S + // NC + PAD_CFG_NC(GPP_F0), + // NC + PAD_CFG_NC(GPP_F1), + // NC + PAD_CFG_NC(GPP_F2), + // NC + PAD_CFG_NC(GPP_F3), + + // LPSS + // NC + PAD_CFG_NC(GPP_F4), + // NC + PAD_CFG_NC(GPP_F5), + // NC + PAD_CFG_NC(GPP_F6), + // NC + PAD_CFG_NC(GPP_F7), + // NC + PAD_CFG_NC(GPP_F8), + // NC + PAD_CFG_NC(GPP_F9), + + // ISH + // NC + PAD_CFG_NC(GPP_F10), + // NC + PAD_CFG_NC(GPP_F11), + + // EMMC + // NC + PAD_CFG_NC(GPP_F12), + // NC + PAD_CFG_NC(GPP_F13), + // NC + PAD_CFG_NC(GPP_F14), + // NC + PAD_CFG_NC(GPP_F15), + // NC + PAD_CFG_NC(GPP_F16), + // NC + PAD_CFG_NC(GPP_F17), + // NC + PAD_CFG_NC(GPP_F18), + // NC + PAD_CFG_NC(GPP_F19), + // NC + PAD_CFG_NC(GPP_F20), + // NC + PAD_CFG_NC(GPP_F21), + // NC + PAD_CFG_NC(GPP_F22), + + // SDIO/SDXC + // LIGHT_KB_DET# + PAD_CFG_NC(GPP_F23), + +// GPP_G + // SDIO/SDXC + // NC + PAD_CFG_NC(GPP_G0), + // TBT Detect + PAD_CFG_NC(GPP_G1), + // NC + PAD_CFG_NC(GPP_G2), + // ASM1543_I_SEL0 + PAD_CFG_NC(GPP_G3), + // ASM1543_I_SEL1 + PAD_CFG_NC(GPP_G4), + // NC + PAD_CFG_NC(GPP_G5), + // NC + PAD_CFG_NC(GPP_G6), + // NC + PAD_CFG_NC(GPP_G7), +}; + +// Early pad configuration in romstage +static const struct pad_config early_gpio_table[] = { + // LPSS + // UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; + +#endif + +#endif diff --git a/src/mainboard/system76/kbl-u/pei_data.c b/src/mainboard/system76/kbl-u/pei_data.c new file mode 100644 index 0000000000..f092f3eb15 --- /dev/null +++ b/src/mainboard/system76/kbl-u/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include "pei_data.h" + +void mainboard_fill_dq_map_data(void *dq_map_ptr) { + /* DQ byte map */ + const u8 dq_map[2][12] = { + {0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0, + 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00}, + {0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC, + 0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00} + }; + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); +} + +void mainboard_fill_dqs_map_data(void *dqs_map_ptr) { + /* DQS CPU<>DRAM map */ + const u8 dqs_map[2][8] = { + {0, 1, 2, 3, 4, 5, 6, 7}, + {1, 0, 2, 3, 4, 5, 6, 7} + }; + memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map)); +} + +void mainboard_fill_rcomp_res_data(void *rcomp_ptr) { + /* Rcomp resistor */ + const u16 RcompResistor[3] = {121, 81, 100}; + memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor)); +} + +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { + /* Rcomp target */ + const u16 RcompTarget[5] = {100, 40, 20, 20, 26}; + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); +} + +void mainboard_fill_pei_data(struct pei_data *pei_data) { + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} diff --git a/src/mainboard/system76/kbl-u/pei_data.h b/src/mainboard/system76/kbl-u/pei_data.h new file mode 100644 index 0000000000..9ad002319e --- /dev/null +++ b/src/mainboard/system76/kbl-u/pei_data.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MAINBOARD_PEI_DATA_H_ +#define _MAINBOARD_PEI_DATA_H_ + +void mainboard_fill_dq_map_data(void *dq_map_ptr); +void mainboard_fill_dqs_map_data(void *dqs_map_ptr); +void mainboard_fill_rcomp_res_data(void *rcomp_ptr); +void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr); + +#endif diff --git a/src/mainboard/system76/kbl-u/ramstage.c b/src/mainboard/system76/kbl-u/ramstage.c new file mode 100644 index 0000000000..40b37b9a87 --- /dev/null +++ b/src/mainboard/system76/kbl-u/ramstage.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_SIL_UPD *params) { + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static void mainboard_init(struct device *dev) { + printk(BIOS_INFO, "system76: keyboard init\n"); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) { + dev->ops->init = mainboard_init; + + // Configure pad for DisplayPort + uint32_t config = 0x44000200; + + uint8_t nvram = 0; + if (get_option(&nvram, "DisplayPort_Output") == CB_SUCCESS) { + if (nvram) { + config |= 1; + } + } + + if (nvram) { + printk(BIOS_INFO, "system76: DisplayPort_Output set to USB-C: 0x%x\n", config); + } else { + printk(BIOS_INFO, "system76: DisplayPort_Output set to Mini_DisplayPort: 0x%x\n", config); + } + + struct pad_config displayport_gpio_table[] = { + /* PS8338B_SW */ + _PAD_CFG_STRUCT(GPP_A22, config, 0x0), + }; + gpio_configure_pads(displayport_gpio_table, ARRAY_SIZE(displayport_gpio_table)); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/system76/kbl-u/romstage.c b/src/mainboard/system76/kbl-u/romstage.c new file mode 100644 index 0000000000..1537f96a2a --- /dev/null +++ b/src/mainboard/system76/kbl-u/romstage.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "pei_data.h" + +void mainboard_memory_init_params(FSPM_UPD *mupd) { + FSP_M_CONFIG *mem_cfg; + struct spd_block blk = { + .addr_map = {0x50, 0x52}, + }; + + mem_cfg = &mupd->FspmConfig; + + get_spd_smbus(&blk); + dump_spd_info(&blk); + assert(blk.spd_array[0][0] != 0); + + mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); + mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); + mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); + mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); + + mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->MemorySpdDataLen = blk.len; + mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; + mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; +} diff --git a/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c new file mode 100644 index 0000000000..23ce3e9f0e --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp2/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x15581303, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581303), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c new file mode 100644 index 0000000000..f346acd917 --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3-b/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x15581414, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581414), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c new file mode 100644 index 0000000000..70a90de7fd --- /dev/null +++ b/src/mainboard/system76/kbl-u/variants/galp3/hda_verb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC269VC */ + 0x10ec0269, /* Vendor ID */ + 0x15581313, /* Subsystem ID */ + 11, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581313), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x14, 0x90170120), + AZALIA_PIN_CFG(0, 0x15, 0x02211010), + AZALIA_PIN_CFG(0, 0x17, 0x40000000), + AZALIA_PIN_CFG(0, 0x18, 0x02a11030), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40f4a205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/thelio-b1/Kconfig b/src/mainboard/system76/thelio-b1/Kconfig new file mode 100644 index 0000000000..f41005aeb7 --- /dev/null +++ b/src/mainboard/system76/thelio-b1/Kconfig @@ -0,0 +1,85 @@ +if BOARD_SYSTEM76_THELIO_B1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_16384 + select EC_ACPI + select EXCLUDE_EMMC_INTERFACE + select FSP_USE_REPO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LPC_TPM + select MAINBOARD_HAS_TPM2 + select MAINBOARD_USES_IFD_GBE_REGION + select SOC_INTEL_CANNONLAKE_PCH_H + select SOC_INTEL_COFFEELAKE + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SPD_READ_BY_WORD + select SYSTEM_TYPE_DESKTOP + select USE_BLOBS + +config MAINBOARD_DIR + string + default system76/thelio-b1 + +config MAINBOARD_PART_NUMBER + string + default "thelio-b1" + +config CBFS_SIZE + hex + default 0xA00000 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1458 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0xa0c3 + +config CONSOLE_POST + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config MAX_CPUS + int + default 16 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_FILE + string + default "pci8086,3e98.rom" + +config VGA_BIOS_ID + string + default "8086,3e98" + +config PXE_ROM_ID + string + default "8086,1539" + +config FSP_M_XIP + bool + default y + +config POST_DEVICE + bool + default n + +endif diff --git a/src/mainboard/system76/thelio-b1/Kconfig.name b/src/mainboard/system76/thelio-b1/Kconfig.name new file mode 100644 index 0000000000..6686fb34a3 --- /dev/null +++ b/src/mainboard/system76/thelio-b1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SYSTEM76_THELIO_B1 + bool "thelio-b1" diff --git a/src/mainboard/system76/thelio-b1/Makefile.inc b/src/mainboard/system76/thelio-b1/Makefile.inc new file mode 100644 index 0000000000..aa8029d385 --- /dev/null +++ b/src/mainboard/system76/thelio-b1/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += ramstage.c hda_verb.c diff --git a/src/mainboard/system76/thelio-b1/acpi_tables.c b/src/mainboard/system76/thelio-b1/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/system76/thelio-b1/board_info.txt b/src/mainboard/system76/thelio-b1/board_info.txt new file mode 100644 index 0000000000..18b9022088 --- /dev/null +++ b/src/mainboard/system76/thelio-b1/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: thelio-b1 +Category: desktop +Release year: 2019 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/thelio-b1/devicetree.cb b/src/mainboard/system76/thelio-b1/devicetree.cb new file mode 100644 index 0000000000..02767d853f --- /dev/null +++ b/src/mainboard/system76/thelio-b1/devicetree.cb @@ -0,0 +1,242 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + +# ACPI (soc/intel/cannonlake/acpi.c) + # Enable s0ix + register "s0ix_enable" = "0" + + # PM Timer Enabled + register "PmTimerDisabled" = "0" + + # Disable DPTF + register "dptf_enable" = "0" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + #register "tdp_pl1_override" = "15" + #register "tdp_pl2_override" = "25" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + register "VmxEnable" = "1" + #register "enable_c6dram" = "1" + register "DebugConsent" = "DebugConsent_Disabled" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # SATA + register "SataMode" = "Sata_AHCI" + register "SataSalpSupport" = "0" + + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "1" + register "SataPortsEnable[4]" = "1" + register "SataPortsEnable[5]" = "1" + register "SataPortsEnable[6]" = "0" + register "SataPortsEnable[7]" = "0" + + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataPortsDevSlp[3]" = "0" + register "SataPortsDevSlp[4]" = "0" + register "SataPortsDevSlp[5]" = "0" + register "SataPortsDevSlp[6]" = "0" + register "SataPortsDevSlp[7]" = "0" + + # Audio + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkSsp2" = "0" + register "PchHdaAudioLinkSndw1" = "0" + register "PchHdaAudioLinkSndw2" = "0" + register "PchHdaAudioLinkSndw3" = "0" + register "PchHdaAudioLinkSndw4" = "0" + + # USB + register "SsicPortEnable" = "0" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A P2 + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C + register "usb2_ports[3]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # F USB 3.0 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0 + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # R USB 3.0 + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # F USB 1 + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.1 P4 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P5 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P6 + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P7 + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB 3.0 P8 + register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC + + # PCI Express Root port #5 x1, Clock 6 (I219-V) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[6]" = "4" + register "PcieClkSrcClkReq[6]" = "6" + + # PCI Express Root port #6 x1, Clock 7 (I211-AT) + register "PcieRpEnable[5]" = "1" + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[7]" = "5" + register "PcieClkSrcClkReq[7]" = "7" + + # PCI Express Root port #9 x4, Clock 5 (M.2 P) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[5]" = "8" + register "PcieClkSrcClkReq[5]" = "5" + + # PCI Express Root port #21 x4, Clock 3 (M.2 Q) + register "PcieRpEnable[20]" = "1" + register "PcieRpLtrEnable[20]" = "1" + register "PcieClkSrcUsage[3]" = "20" + register "PcieClkSrcClkReq[3]" = "3" + + # TODO: Clock 0 is used for PCIE X16 + + # Misc + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "AcousticNoiseMitigation" = "1" + #register "dmipwroptimize" = "1" + #register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + + # Serial IRQ Continuous + register "SerialIrqConfigSirqMode" = "1" + +# LPC (soc/intel/cannonlake/lpc.c) + # LPC configuration from lspci -xxx + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x00040069" + register "gen3_dec" = "0x000c3321" + register "gen4_dec" = "0x00000000" + + # 8254 + register "clock_gate_8254" = "0" + +# PMC (soc/intel/cannonlake/pmc.c) + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "0" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + #chip drivers/intel/wifi + # register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + #end + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/system76/thelio-b1/dsdt.asl b/src/mainboard/system76/thelio-b1/dsdt.asl new file mode 100644 index 0000000000..d37c726c51 --- /dev/null +++ b/src/mainboard/system76/thelio-b1/dsdt.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include + + // global NVS and variables + #include + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + // Chipset specific sleep states + #include + + Scope (\_SB.PCI0.LPCB) + { + /* ACPI code for EC SuperIO functions */ + #include + } +} diff --git a/src/mainboard/system76/thelio-b1/gpio.h b/src/mainboard/system76/thelio-b1/gpio.h new file mode 100644 index 0000000000..c6f9fdf436 --- /dev/null +++ b/src/mainboard/system76/thelio-b1/gpio.h @@ -0,0 +1,607 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +// GPD + // Power Management + // N_-BATLOW + _PAD_CFG_STRUCT(GPD0, 0x4000600, 0x0), + // N_GP_D1 + _PAD_CFG_STRUCT(GPD1, 0x4000700, 0x3c00), + // N_-LAN_WAKE + _PAD_CFG_STRUCT(GPD2, 0x80500, 0x3c00), + // O_PWRBTSW + _PAD_CFG_STRUCT(GPD3, 0x4000500, 0x3000), + // N_-SLP_S3 + _PAD_CFG_STRUCT(GPD4, 0x4000600, 0x0), + // N_-S4_S5 + _PAD_CFG_STRUCT(GPD5, 0x4000600, 0x0), + // N_-SLP_A + _PAD_CFG_STRUCT(GPD6, 0x4000600, 0x0), + + // GPIO + // N_GPD_7 + _PAD_CFG_STRUCT(GPD7, 0x4000200, 0x0), + + // Power Management + // N_SUSCLK + _PAD_CFG_STRUCT(GPD8, 0x4000600, 0x0), + // NC + _PAD_CFG_STRUCT(GPD9, 0x4000600, 0x0), + // N_-SLP_S5 + _PAD_CFG_STRUCT(GPD10, 0x4000600, 0x0), + // N_-LAN_DIS + _PAD_CFG_STRUCT(GPD11, 0x4000600, 0x0), + +// GPP_A + // LPC + // N_-KBRST + _PAD_CFG_STRUCT(GPP_A0, 0x44000700, 0x0), + // N_LAD0 + _PAD_CFG_STRUCT(GPP_A1, 0x44000700, 0x3c00), + // N_LAD1 + _PAD_CFG_STRUCT(GPP_A2, 0x44000700, 0x3c00), + // N_LAD2 + _PAD_CFG_STRUCT(GPP_A3, 0x44000700, 0x3c00), + // N_LAD3 + _PAD_CFG_STRUCT(GPP_A4, 0x44000700, 0x3c00), + // N_-LFRAME + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0), + // N_SERIRQ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x0), + // N_-LDRQ0 + _PAD_CFG_STRUCT(GPP_A7, 0x44000700, 0x0), + // N_GPP_A8 + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0), + // T_TPMCLK + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), + // N_LPC24MA + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), + + // Power Management + // NC + _PAD_CFG_STRUCT(GPP_A11, 0x44000700, 0x3000), + // N_GPP_A12 + _PAD_CFG_STRUCT(GPP_A12, 0x44000300, 0x0), + // N_-S_WARN + _PAD_CFG_STRUCT(GPP_A13, 0x44000700, 0x0), + + // LPC + // N_GPP_A14 + _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0), + + // Power Management + // N_-S_ACK + _PAD_CFG_STRUCT(GPP_A15, 0x44000700, 0x3000), + + // Clock Signals + // N_GPP_A16 + _PAD_CFG_STRUCT(GPP_A16, 0x44000300, 0x0), + + // ISH + // NC + _PAD_CFG_STRUCT(GPP_A17, 0x84000201, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_A18, 0x84000201, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_A19, 0x84000201, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_A20, 0x84000201, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_A21, 0x84000201, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x0), + +// GPP_B + // GSPI + // N_-DDR_V_SEL + _PAD_CFG_STRUCT(GPP_B0, 0x40000700, 0x0), + // NTP104 + _PAD_CFG_STRUCT(GPP_B1, 0x44000300, 0x0), + + // Power Management + // N_-VRALERT + _PAD_CFG_STRUCT(GPP_B2, 0x44000300, 0x0), + + // CPU Misc + // N_GPP_B3 + _PAD_CFG_STRUCT(GPP_B3, 0x44000300, 0x0), + // N_GPP_B4 + _PAD_CFG_STRUCT(GPP_B4, 0x84000101, 0x0), + + // Clock Signals + // -PCIEX16_PR + _PAD_CFG_STRUCT(GPP_B5, 0x84000101, 0x0), + // N_GPP_B6 + _PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x0), + // N_GPP_B7 + _PAD_CFG_STRUCT(GPP_B7, 0x44000300, 0x0), + // M2Q_-CLKREQ + _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0), + // N_GPP_B9 + _PAD_CFG_STRUCT(GPP_B9, 0x44000700, 0x0), + // M2P_-CLKREQ + _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0), + + // Audio + // NTP106 + _PAD_CFG_STRUCT(GPP_B11, 0x44000700, 0x0), + + // Power Management + // N_-SLP_S0 + _PAD_CFG_STRUCT(GPP_B12, 0x4000100, 0x0), + // N_-PFMRST + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0), + + // Audio + // N_SPKR + _PAD_CFG_STRUCT(GPP_B14, 0x44000700, 0x0), + + // GSPI + // N_GPP_B15 + _PAD_CFG_STRUCT(GPP_B15, 0x44000600, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_B16, 0x84000101, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_B17, 0x84000101, 0x0), + // N_GPP_B18 + _PAD_CFG_STRUCT(GPP_B18, 0x84000101, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_B19, 0x44000200, 0x0), + // N_GPP_B20 + _PAD_CFG_STRUCT(GPP_B20, 0x4000100, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_B21, 0x82000301, 0x0), + // N_GPP_B22 + _PAD_CFG_STRUCT(GPP_B22, 0x84000101, 0x0), + + // SMBUS + // N_-PCH_HOT + _PAD_CFG_STRUCT(GPP_B23, 0x44000200, 0x0), + +// GPP_C + // SMBUS + // N_SMBCLK + _PAD_CFG_STRUCT(GPP_C0, 0x44000700, 0x0), + // N_SMBDATA + _PAD_CFG_STRUCT(GPP_C1, 0x44000700, 0x0), + // N_-LPCPME + _PAD_CFG_STRUCT(GPP_C2, 0x44000200, 0x0), + // N_SML0CLK + _PAD_CFG_STRUCT(GPP_C3, 0x44000700, 0x0), + // N_SML0DAT + _PAD_CFG_STRUCT(GPP_C4, 0x44000700, 0x0), + // N_GPP_C5 + _PAD_CFG_STRUCT(GPP_C5, 0x44000200, 0x0), + // N_SML1CLK + _PAD_CFG_STRUCT(GPP_C6, 0x44000300, 0x0), + // N_SML1DAT + _PAD_CFG_STRUCT(GPP_C7, 0x44000300, 0x0), + + // UART + // N_GPP_C8 + _PAD_CFG_STRUCT(GPP_C8, 0x44000300, 0x0), + // N_GPP_C9 + _PAD_CFG_STRUCT(GPP_C9, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_C10, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_C11, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_C12, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_C13, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_C14, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_C15, 0x44000300, 0x0), + + // I2C + // NTP127 + _PAD_CFG_STRUCT(GPP_C16, 0x44000300, 0x0), + // NTP126 + _PAD_CFG_STRUCT(GPP_C17, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_C18, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_C19, 0x44000300, 0x0), + + // UART + // NC + _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x0), + // N_GPP_C21 + _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x0), + // N_GPP_C22 + _PAD_CFG_STRUCT(GPP_C22, 0x44000300, 0x0), + // N_GPP_C23 + _PAD_CFG_STRUCT(GPP_C23, 0x44000300, 0x0), + +// GPP_D + // SPI + // NC + _PAD_CFG_STRUCT(GPP_D0, 0x84000200, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D1, 0x84000200, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D2, 0x84000200, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D3, 0x44000100, 0x0), + + // I2C + // N_GPP_D_4 + _PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x0), + + // CNVI + // -CNVI_RF_RESET + _PAD_CFG_STRUCT(GPP_D5, 0x44000f00, 0x0), + // CNVI_CLKREQ + _PAD_CFG_STRUCT(GPP_D6, 0x44000f00, 0x0), + // CNVI_PCM_IN + _PAD_CFG_STRUCT(GPP_D7, 0x44000f00, 0x0), + // -CNVI_PCM_CLK + _PAD_CFG_STRUCT(GPP_D8, 0x44000f00, 0x0), + + // ISH + // N_GPP_D9 + _PAD_CFG_STRUCT(GPP_D9, 0x84000200, 0x0), + // N_GPP_D10 + _PAD_CFG_STRUCT(GPP_D10, 0x44000300, 0x0), + // N_GPP_D11 + _PAD_CFG_STRUCT(GPP_D11, 0x44001700, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D12, 0x44001700, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D13, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D14, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D15, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D16, 0x44000300, 0x0), + + // DMIC + // NC + _PAD_CFG_STRUCT(GPP_D17, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D18, 0x44000300, 0x0), + // N_GPP_D19 + _PAD_CFG_STRUCT(GPP_D19, 0x4000200, 0x0), + // N_GPP_D20 + _PAD_CFG_STRUCT(GPP_D20, 0x44000300, 0x0), + + // SPI + // N_GPP_D21 + _PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x0), + + // ISH + // N_GPP_D23 + _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x0), + +// GPP_E + // SATA + // N_GPP_E0 + _PAD_CFG_STRUCT(GPP_E0, 0x84000500, 0x3000), + // N_GPP_E1 + _PAD_CFG_STRUCT(GPP_E1, 0x84000500, 0x3000), + // N_GPP_E2 + _PAD_CFG_STRUCT(GPP_E2, 0x84000500, 0x3000), + + // CPU Misc + // NC + _PAD_CFG_STRUCT(GPP_E3, 0x44000300, 0x0), + + // SATA + // N_DEVSLP0 + _PAD_CFG_STRUCT(GPP_E4, 0x44000500, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_E5, 0x44000500, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_E6, 0x44000500, 0x0), + + // CPU Misc + // NC + _PAD_CFG_STRUCT(GPP_E7, 0x44000300, 0x0), + + // SATA + // N_-SATALED + _PAD_CFG_STRUCT(GPP_E8, 0x44000700, 0x0), + + // USB2 + // N_-USBOC_R + _PAD_CFG_STRUCT(GPP_E9, 0x44000500, 0x0), + // N_-USBOC_F + _PAD_CFG_STRUCT(GPP_E10, 0x44000500, 0x0), + // N_-USBOC_F + _PAD_CFG_STRUCT(GPP_E11, 0x44000500, 0x0), + // N_-USBOC_R + _PAD_CFG_STRUCT(GPP_E12, 0x44000500, 0x0), + +// GPP_F + // SATA + // N_GPP_F0 + _PAD_CFG_STRUCT(GPP_F0, 0x84000500, 0x3000), + // N_GPP_F1 + _PAD_CFG_STRUCT(GPP_F1, 0x84000500, 0x3000), + // N_GPP_F2 + _PAD_CFG_STRUCT(GPP_F2, 0x84000500, 0x3000), + // N_GPP_F3 + _PAD_CFG_STRUCT(GPP_F3, 0x44000700, 0x0), + // N_GPP_F4 + _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x0), + // N_GPP_F5 + _PAD_CFG_STRUCT(GPP_F5, 0x44000500, 0x0), + // N_DEVSLP4 + _PAD_CFG_STRUCT(GPP_F6, 0x44000500, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_F7, 0x44000500, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_F8, 0x44000500, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_F9, 0x44000500, 0x0), + // N_GPP_F10 + _PAD_CFG_STRUCT(GPP_F10, 0x84000100, 0x0), + // N_GPP_F11 + _PAD_CFG_STRUCT(GPP_F11, 0x44000300, 0x0), + // N_GPP_F12 + _PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x0), + // N_GPP_F13 + _PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x0), + + // Power Management + // NTP124 + _PAD_CFG_STRUCT(GPP_F14, 0x44000b00, 0x0), + + // USB2 + // N_-USBOC_F + _PAD_CFG_STRUCT(GPP_F15, 0x44000500, 0x0), + // N_-USBOC_7 + _PAD_CFG_STRUCT(GPP_F16, 0x44000500, 0x0), + // N_-USBOC_7 + _PAD_CFG_STRUCT(GPP_F17, 0x44000500, 0x0), + // N_-USBOC_7 + _PAD_CFG_STRUCT(GPP_F18, 0x44000500, 0x0), + + // Display Signals + // NC + _PAD_CFG_STRUCT(GPP_F19, 0x44000700, 0x0), + // NTP88 + _PAD_CFG_STRUCT(GPP_F20, 0x44000700, 0x0), + // NTP87 + _PAD_CFG_STRUCT(GPP_F21, 0x44000700, 0x0), + // N_GPP_F22 + _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x0), + // N_GPP_F23 + _PAD_CFG_STRUCT(GPP_F23, 0x44000200, 0x0), + +// GPP_G + // SD + // NC + _PAD_CFG_STRUCT(GPP_G0, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_G1, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_G2, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_G3, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_G4, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_G5, 0x44000300, 0x0), + // N_GPPC_G6 + _PAD_CFG_STRUCT(GPP_G6, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_G7, 0x44000300, 0x0), + +// GPP_H + // Clock Signals + // LB_-CLKREQ + _PAD_CFG_STRUCT(GPP_H0, 0x44000700, 0x0), + // N_GPP_H1 + _PAD_CFG_STRUCT(GPP_H1, 0x44000100, 0x0), + // N_GPP_H2 + _PAD_CFG_STRUCT(GPP_H2, 0x44000300, 0x0), + // N_GPP_H3 + _PAD_CFG_STRUCT(GPP_H3, 0x44000300, 0x0), + // N_GPP_H4 + _PAD_CFG_STRUCT(GPP_H4, 0x44000300, 0x0), + // N_GPP_H5 + _PAD_CFG_STRUCT(GPP_H5, 0x44000300, 0x0), + // N_GPP_H6 + _PAD_CFG_STRUCT(GPP_H6, 0x44000300, 0x0), + // N_GPP_H7 + _PAD_CFG_STRUCT(GPP_H7, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_H8, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_H9, 0x44000300, 0x0), + + // SMBUS + // NC + _PAD_CFG_STRUCT(GPP_H10, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_H11, 0x44000300, 0x0), + // N_GPP_H12 + _PAD_CFG_STRUCT(GPP_H12, 0x44000200, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_H13, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_H14, 0x44000300, 0x0), + // N_GPP_H15 + _PAD_CFG_STRUCT(GPP_H15, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_H16, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_H17, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_H18, 0x44000300, 0x0), + + // ISH + // N_GPP_H19 + _PAD_CFG_STRUCT(GPP_H19, 0x44000300, 0x0), + // N_GPP_H20 + _PAD_CFG_STRUCT(GPP_H20, 0x44000300, 0x0), + // N_GPP_H21 + _PAD_CFG_STRUCT(GPP_H21, 0x44000300, 0x0), + // N_GPP_H22 + _PAD_CFG_STRUCT(GPP_H22, 0x44000300, 0x0), + + // GPIO + // NC + _PAD_CFG_STRUCT(GPP_H23, 0x44000300, 0x0), + +// GPP_I + // Display Signals + // N_HDMI_HDP_F + _PAD_CFG_STRUCT(GPP_I0, 0x40000700, 0x3c00), + // N_HDMI20_HDP_F + _PAD_CFG_STRUCT(GPP_I1, 0x40000700, 0x3c00), + // DP_HDP + _PAD_CFG_STRUCT(GPP_I2, 0x40000700, 0x3c00), + // N_GPP_I3 + _PAD_CFG_STRUCT(GPP_I3, 0x40000700, 0x0), + // N_GPP_I4 + _PAD_CFG_STRUCT(GPP_I4, 0x40000700, 0x0), + // N_DDPB_CTRLCLK + _PAD_CFG_STRUCT(GPP_I5, 0x40000700, 0x0), + // N_DDPB_CTRLDATA + _PAD_CFG_STRUCT(GPP_I6, 0x40000700, 0x0), + // N_DDPC_CTRLCLK + _PAD_CFG_STRUCT(GPP_I7, 0x40000700, 0x0), + // N_DDPC_CTRLDATA + _PAD_CFG_STRUCT(GPP_I8, 0x40000700, 0x0), + // N_DDPD_CTRLCLK + _PAD_CFG_STRUCT(GPP_I9, 0x40000700, 0x1000), + // N_DDPD_CTRLDATA + _PAD_CFG_STRUCT(GPP_I10, 0x40000700, 0x1000), + + // PCIE + // A_-SKTOCC + _PAD_CFG_STRUCT(GPP_I11, 0x40000700, 0x3c00), + // NC + _PAD_CFG_STRUCT(GPP_I12, 0x40000700, 0x3c00), + // NC + _PAD_CFG_STRUCT(GPP_I13, 0x40000700, 0x3c00), + // NC + _PAD_CFG_STRUCT(GPP_I14, 0x40000700, 0x3c00), + +// GPP_J + // CNVI + // CNVI_PA_BLANKING + _PAD_CFG_STRUCT(GPP_J0, 0x40000700, 0x3c00), + + // Power Management + // CPU_VCCIO_PW R_GATEB + _PAD_CFG_STRUCT(GPP_J1, 0x40000700, 0x3c00), + + // GPIO + // NC + _PAD_CFG_STRUCT(GPP_J2, 0x40000700, 0x3c00), + // NC + _PAD_CFG_STRUCT(GPP_J3, 0x40000700, 0x3c00), + + // CNVI + // CNVI_BRI_DT + _PAD_CFG_STRUCT(GPP_J4, 0x40000700, 0x3c00), + // CNVI_BRI_RSP + _PAD_CFG_STRUCT(GPP_J5, 0x44000500, 0x0), + // CNVI_RGI_DT + _PAD_CFG_STRUCT(GPP_J6, 0x44000500, 0x0), + // CNVI_RGI_RSP + _PAD_CFG_STRUCT(GPP_J7, 0x44000500, 0x0), + // CNVI_MFUART2_RXD + _PAD_CFG_STRUCT(GPP_J8, 0x44000500, 0x0), + // CNVI_MFUART2_TXD + _PAD_CFG_STRUCT(GPP_J9, 0x44000500, 0x0), + + // GPIO + // NC + _PAD_CFG_STRUCT(GPP_J10, 0x44000500, 0x0), + + // A4WP + // NTP122 + _PAD_CFG_STRUCT(GPP_J11, 0x44000600, 0x0), + +// GPP_K + // GPIO + // N_GPP_K0 + _PAD_CFG_STRUCT(GPP_K0, 0x4000100, 0x0), + // N_GPP_K1 + _PAD_CFG_STRUCT(GPP_K1, 0x4000100, 0x0), + // N_GPP_K2 + _PAD_CFG_STRUCT(GPP_K2, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K3, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K4, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K5, 0x44000300, 0x0), + // N_GPP_K6 + _PAD_CFG_STRUCT(GPP_K6, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K7, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K8, 0x44000700, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K9, 0x44000700, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K10, 0x44000700, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K11, 0x44000700, 0x0), + + // GSX + // NC + _PAD_CFG_STRUCT(GPP_K12, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K13, 0x44000300, 0x0), + // N_GT_S + _PAD_CFG_STRUCT(GPP_K14, 0x44000300, 0x0), + // N_CPU_S + _PAD_CFG_STRUCT(GPP_K15, 0x44000300, 0x0), + // M2_BT_DISABLE + _PAD_CFG_STRUCT(GPP_K16, 0x44000300, 0x0), + + // GPIO + // M2_WIFI_DISABLE + _PAD_CFG_STRUCT(GPP_K17, 0x44000300, 0x0), + // N_GPP_K18 + _PAD_CFG_STRUCT(GPP_K18, 0x44000300, 0x0), + // N_GPP_K19 + _PAD_CFG_STRUCT(GPP_K19, 0x44000300, 0x0), + // N_GPP_K20 + _PAD_CFG_STRUCT(GPP_K20, 0x44000700, 0x0), + // N_GPP_K21 + _PAD_CFG_STRUCT(GPP_K21, 0x44000700, 0x0), + // N_GPP_K22 + _PAD_CFG_STRUCT(GPP_K22, 0x44000300, 0x0), + // NC + _PAD_CFG_STRUCT(GPP_K23, 0x44000300, 0x0), +}; + +#endif + +#endif diff --git a/src/mainboard/system76/thelio-b1/hda_verb.c b/src/mainboard/system76/thelio-b1/hda_verb.c new file mode 100644 index 0000000000..0d4c13ac20 --- /dev/null +++ b/src/mainboard/system76/thelio-b1/hda_verb.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC1220 */ + 0x10ec1220, /* Vendor ID */ + 0x1458a0c3, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1458a0c3), + AZALIA_PIN_CFG(0, 0x12, 0x403fc000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x411111f0), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1d, 0x4047c669), + AZALIA_PIN_CFG(0, 0x1e, 0x99430130), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/thelio-b1/ramstage.c b/src/mainboard/system76/thelio-b1/ramstage.c new file mode 100644 index 0000000000..6572aadb45 --- /dev/null +++ b/src/mainboard/system76/thelio-b1/ramstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/system76/thelio-b1/romstage.c b/src/mainboard/system76/thelio-b1/romstage.c new file mode 100644 index 0000000000..0cb3ada706 --- /dev/null +++ b/src/mainboard/system76/thelio-b1/romstage.c @@ -0,0 +1,97 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +//TODO: find correct values +static const struct cnl_mb_cfg memcfg = { + /* + * For each channel, there are 3 sets of DQ byte mappings, + * where each set has a package 0 and a package 1 value (package 0 + * represents the first 64-bit lpddr4 chip combination, and package 1 + * represents the second 64-bit lpddr4 chip combination). + * The first three sets are for CLK, CMD, and CTL. + * The fsp package actually expects 6 sets, but the last 3 sets are + * not used in CNL, so we only define the three sets that are used + * and let the meminit_lpddr4() routine take care of clearing the + * unused fields for the caller. + */ + // These settings are ignored unless you are using LPDDR4 + .dq_map[DDR_CH0] = { + {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0}, + //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + .dq_map[DDR_CH1] = { + {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC}, + //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + + /* + * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + // These settings are ignored unless you are using LPDDR4 + .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + // These are the recommended settings for CFL-S + .rcomp_resistor = { 121, 75, 100 }, + + /* + * Rcomp target values. These will typically be the following + * values for Cannon Lake : { 80, 40, 40, 40, 30 } + */ + // These are the recommended settings for CFL-S + .rcomp_targets = { 60, 26, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + // TODO: Find correct settings + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuraation. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + // These are the recommended settings for DDR4 + .vref_ca_config = 2, + + /* Early Command Training Enabled */ + // TODO: Find correct settings + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct spd_info spd = { + .spd_smbus_address[0] = 0xA0, + .spd_smbus_address[2] = 0xA4, + }; + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd); +} diff --git a/src/mainboard/system76/whl-u/Kconfig b/src/mainboard/system76/whl-u/Kconfig new file mode 100644 index 0000000000..5e423b189a --- /dev/null +++ b/src/mainboard/system76/whl-u/Kconfig @@ -0,0 +1,107 @@ +if BOARD_SYSTEM76_GALP3_C || BOARD_SYSTEM76_DARP5 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ADD_FSP_BINARIES + select BOARD_ROMSIZE_KB_16384 + select EC_ACPI + select EXCLUDE_EMMC_INTERFACE + select FSP_USE_REPO + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select HAVE_SMI_HANDLER + select INTEL_GMA_HAVE_VBT +# select MAINBOARD_HAS_SPI_TPM_CR50 +# select MAINBOARD_HAS_TPM2 + select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_WHISKEYLAKE + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select USE_BLOBS + select USE_OPTION_TABLE + +config MAINBOARD_DIR + string + default system76/whl-u + +config VARIANT_DIR + string + default "galp3-c" if BOARD_SYSTEM76_GALP3_C + default "darp5" if BOARD_SYSTEM76_DARP5 + +config MAINBOARD_PART_NUMBER + string + default "galp3-c" if BOARD_SYSTEM76_GALP3_C + default "darp5" if BOARD_SYSTEM76_DARP5 + +config CBFS_SIZE + hex + default 0xA00000 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1558 + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x1323 if BOARD_SYSTEM76_GALP3_C + default 0x1325 if BOARD_SYSTEM76_DARP5 + +config CONSOLE_POST + bool + default y + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +# This causes UEFI to hang +#config UART_FOR_CONSOLE +# int +# default 2 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_FILE + string + default "pci8086,3ea0.rom" + +config VGA_BIOS_ID + string + default "8086,3ea0" + +config PXE_ROM_ID + string + default "10ec,8168" + +config FSP_M_XIP + bool + default y + +config POST_DEVICE + bool + default n + +#config DRIVER_TPM_SPI_BUS +# hex +# default 0x0 + +#config DRIVER_TPM_SPI_CHIP +# int +# default 2 + +endif diff --git a/src/mainboard/system76/whl-u/Kconfig.name b/src/mainboard/system76/whl-u/Kconfig.name new file mode 100644 index 0000000000..6379e79abb --- /dev/null +++ b/src/mainboard/system76/whl-u/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_SYSTEM76_GALP3_C + bool "galp3-c" + +config BOARD_SYSTEM76_DARP5 + bool "darp5" diff --git a/src/mainboard/system76/whl-u/Makefile.inc b/src/mainboard/system76/whl-u/Makefile.inc new file mode 100644 index 0000000000..e9e47a7ff0 --- /dev/null +++ b/src/mainboard/system76/whl-u/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += ramstage.c variants/$(VARIANT_DIR)/hda_verb.c diff --git a/src/mainboard/system76/whl-u/acpi/ac.asl b/src/mainboard/system76/whl-u/acpi/ac.asl new file mode 100644 index 0000000000..7a55e45ca3 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/ac.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (AC) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) // _HID: Hardware ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Return (ACFG) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } +} diff --git a/src/mainboard/system76/whl-u/acpi/battery.asl b/src/mainboard/system76/whl-u/acpi/battery.asl new file mode 100644 index 0000000000..bfda8a00cd --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/battery.asl @@ -0,0 +1,183 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (BFCC, Zero) + Method (_STA, 0, NotSerialized) // _STA: Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package (0x0D) + { + One, + 0xFFFFFFFF, + 0xFFFFFFFF, + One, + 0x39D0, + Zero, + Zero, + 0x40, + 0x40, + "BAT", + "0001", + "LION", + "Notebook" + }) + Method (IVBI, 0, NotSerialized) + { + PBIF [One] = 0xFFFFFFFF + PBIF [0x02] = 0xFFFFFFFF + PBIF [0x04] = 0xFFFFFFFF + PBIF [0x09] = " " + PBIF [0x0A] = " " + PBIF [0x0B] = " " + PBIF [0x0C] = " " + BFCC = Zero + } + + Method (UPBI, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF) + PBIF [One] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF) + PBIF [0x02] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF) + PBIF [0x04] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF) + PBIF [0x05] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF) + PBIF [0x06] = Local0 + PBIF [0x09] = "BAT" + PBIF [0x0A] = "0001" + PBIF [0x0B] = "LION" + PBIF [0x0C] = "Notebook" + } + Else + { + IVBI () + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBI () + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Name (PBST, Package (0x04) + { + Zero, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0x3D90 + }) + Method (IVBS, 0, NotSerialized) + { + PBST [Zero] = Zero + PBST [One] = 0xFFFFFFFF + PBST [0x02] = 0xFFFFFFFF + PBST [0x03] = 0x2710 + } + + Method (UPBS, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = Zero + Local1 = Zero + If (^^AC.ACFG) + { + If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02)) + { + Local0 |= 0x02 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + } + Else + { + Local0 |= One + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + + Local7 = (Local1 & 0x8000) + If ((Local7 == 0x8000)) + { + Local1 ^= 0xFFFF + } + + Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF) + Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF) + PBST [Zero] = Local0 + PBST [One] = Local1 + PBST [0x02] = Local2 + PBST [0x03] = Local3 + If ((BFCC != ^^PCI0.LPCB.EC0.BFC0)) + { + Notify (BAT0, 0x81) // Information Change + } + } + Else + { + IVBS () + } + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBS () + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } +} diff --git a/src/mainboard/system76/whl-u/acpi/buttons.asl b/src/mainboard/system76/whl-u/acpi/buttons.asl new file mode 100644 index 0000000000..4b5940333e --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/buttons.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 }) +} + +Device (SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 }) +} diff --git a/src/mainboard/system76/whl-u/acpi/ec.asl b/src/mainboard/system76/whl-u/acpi/ec.asl new file mode 100644 index 0000000000..ae0796e9ee --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/ec.asl @@ -0,0 +1,216 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) // _HID: Hardware ID + Name (_GPE, 0x50 /* GPP_E16 */) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + + #include "acpi/ec_ram.asl" + + Name (ECOK, Zero) + Method (_REG, 2, Serialized) // _REG: Region Availability + { + Debug = Concatenate("EC: _REG", Concatenate(ToHexString(Arg0), Concatenate(" ", ToHexString(Arg1)))) + If (((Arg0 == 0x03) && (Arg1 == One))) { + // Enable software touchpad lock and airplane mode keys + ECOS = 2 + + // Enable software backlight keys + WINF = 1 + + // Set current AC state + ^^^^AC.ACFG = ADP + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + PNOT () + + // EC is now available + ECOK = Arg1 + } + } + + Method (PTS, 1, Serialized) { + Debug = Concatenate("EC: PTS: ", ToHexString(Arg0)) + If (ECOK) { + WFNO = Zero + } + } + + Method (WAK, 1, Serialized) { + Debug = Concatenate("EC: WAK: ", ToHexString(Arg0)) + If (ECOK) { + // Set current AC state + ^^^^AC.ACFG = ADP + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + Notify(^^^^AC, Zero) + Notify(^^^^BAT0, Zero) + } + } + + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle + { + Debug = "EC: Touchpad Toggle" + } + + Method (_Q0B, 0, NotSerialized) // Screen Toggle + { + Debug = "EC: Screen Toggle" + } + + Method (_Q0C, 0, NotSerialized) // Mute + { + Debug = "EC: Mute" + } + + Method (_Q0D, 0, NotSerialized) // Keyboard Backlight + { + Debug = "EC: Keyboard Backlight" + } + + Method (_Q0E, 0, NotSerialized) // Volume Down + { + Debug = "EC: Volume Down" + } + + Method (_Q0F, 0, NotSerialized) // Volume Up + { + Debug = "EC: Volume Up" + } + + Method (_Q10, 0, NotSerialized) // Switch Video Mode + { + Debug = "EC: Switch Video Mode" + } + + Method (_Q11, 0, NotSerialized) // Brightness Down + { + Debug = "EC: Brightness Down" + ^^^^HIDD.HPEM (20) + } + + Method (_Q12, 0, NotSerialized) // Brightness Up + { + Debug = "EC: Brightness Up" + ^^^^HIDD.HPEM (19) + } + + Method (_Q13, 0, NotSerialized) // Camera Toggle + { + Debug = "EC: Camera Toggle" + } + + Method (_Q14, 0, NotSerialized) // Airplane Mode + { + Debug = "EC: Airplane Mode" + ^^^^HIDD.HPEM (8) + } + + Method (_Q15, 0, NotSerialized) // Suspend Button + { + Debug = "EC: Suspend Button" + Notify (SLPB, 0x80) + } + + Method (_Q16, 0, NotSerialized) // AC Detect + { + Debug = "EC: AC Detect" + ^^^^AC.ACFG = ADP + Notify (AC, 0x80) // Status Change + Sleep (0x01F4) + If (BAT0) + { + Notify (^^^^BAT0, 0x81) // Information Change + Sleep (0x32) + Notify (^^^^BAT0, 0x80) // Status Change + Sleep (0x32) + } + } + + Method (_Q17, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (17)" + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q19, 0, NotSerialized) // BAT0 Update + { + Debug = "EC: BAT0 Update (19)" + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q1B, 0, NotSerialized) // Lid Close + { + Debug = "EC: Lid Close" + Notify (LID0, 0x80) + } + + Method (_Q1C, 0, NotSerialized) // Thermal Trip + { + Debug = "EC: Thermal Trip" + /* TODO + Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change + Notify (\_TZ.TZ0, 0x80) // Thermal Status Change + */ + } + + Method (_Q1D, 0, NotSerialized) // Power Button + { + Debug = "EC: Power Button" + Notify (PWRB, 0x80) + } + + Method (_Q50, 0, NotSerialized) // Other Events + { + Local0 = OEM4 + If (Local0 == 0x8A) { + Debug = "EC: White Keyboard Backlight" + Notify (^^^^S76D, 0x80) + } ElseIf (Local0 == 0x9F) { + Debug = "EC: Color Keyboard Toggle" + Notify (^^^^S76D, 0x81) + } ElseIf (Local0 == 0x81) { + Debug = "EC: Color Keyboard Down" + Notify (^^^^S76D, 0x82) + } ElseIf (Local0 == 0x82) { + Debug = "EC: Color Keyboard Up" + Notify (^^^^S76D, 0x83) + } ElseIf (Local0 == 0x80) { + Debug = "EC: Color Keyboard Color Change" + Notify (^^^^S76D, 0x84) + } Else { + Debug = Concatenate("EC: Other: ", ToHexString(Local0)) + } + } +} diff --git a/src/mainboard/system76/whl-u/acpi/ec_ram.asl b/src/mainboard/system76/whl-u/acpi/ec_ram.asl new file mode 100644 index 0000000000..9502f5f057 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/ec_ram.asl @@ -0,0 +1,188 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +OperationRegion (ERAM, EmbeddedControl, Zero, 0xFF) +Field (ERAM, ByteAcc, Lock, Preserve) +{ + NMSG, 8, + SLED, 4, + Offset (0x02), + MODE, 1, + FAN0, 1, + TME0, 1, + TME1, 1, + FAN1, 1, + , 2, + Offset (0x03), + LSTE, 1, + LSW0, 1, + LWKE, 1, + WAKF, 1, + , 2, + PWKE, 1, + MWKE, 1, + AC0, 8, + PSV, 8, + CRT, 8, + TMP, 8, + AC1, 8, + BBST, 8, + Offset (0x0B), + Offset (0x0C), + Offset (0x0D), + Offset (0x0E), + SLPT, 8, + SWEJ, 1, + SWCH, 1, + Offset (0x10), + ADP, 1, + AFLT, 1, + BAT0, 1, + BAT1, 1, + , 3, + PWOF, 1, + WFNO, 8, + BPU0, 32, + BDC0, 32, + BFC0, 32, + BTC0, 32, + BDV0, 32, + BST0, 32, + BPR0, 32, + BRC0, 32, + BPV0, 32, + BTP0, 16, + BRS0, 16, + BCW0, 32, + BCL0, 32, + BCG0, 32, + BG20, 32, + BMO0, 64, + BIF0, 64, + BSN0, 32, + BTY0, 64, + Offset (0x67), + Offset (0x68), + ECOS, 8, + LNXD, 8, + ECPS, 8, + Offset (0x6C), + BTMP, 16, + EVTN, 8, + Offset (0x72), + PRCL, 8, + PRC0, 8, + PRC1, 8, + PRCM, 8, + PRIN, 8, + PSTE, 8, + PCAD, 8, + PEWL, 8, + PWRL, 8, + PECD, 8, + PEHI, 8, + PECI, 8, + PEPL, 8, + PEPM, 8, + PWFC, 8, + PECC, 8, + PDT0, 8, + PDT1, 8, + PDT2, 8, + PDT3, 8, + PRFC, 8, + PRS0, 8, + PRS1, 8, + PRS2, 8, + PRS3, 8, + PRS4, 8, + PRCS, 8, + PEC0, 8, + PEC1, 8, + PEC2, 8, + PEC3, 8, + CMDR, 8, + CVRT, 8, + GTVR, 8, + FANT, 8, + SKNT, 8, + AMBT, 8, + MCRT, 8, + DIM0, 8, + DIM1, 8, + PMAX, 8, + PPDT, 8, + PECH, 8, + PMDT, 8, + TSD0, 8, + TSD1, 8, + TSD2, 8, + TSD3, 8, + CPUP, 16, + MCHP, 16, + SYSP, 16, + CPAP, 16, + MCAP, 16, + SYAP, 16, + CFSP, 16, + CPUE, 16, + Offset (0xC6), + Offset (0xC7), + VGAT, 8, + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, + Offset (0xCE), + DUT1, 8, + DUT2, 8, + RPM1, 16, + RPM2, 16, + RPM4, 16, + Offset (0xD7), + DTHL, 8, + DTBP, 8, + AIRP, 8, + WINF, 8, + RINF, 8, + Offset (0xDD), + INF2, 8, + MUTE, 1, + Offset (0xE0), + RPM3, 16, + ECKS, 8, + Offset (0xE4), + , 4, + XTUF, 1, + EP12, 1, + Offset (0xE5), + INF3, 8, + Offset (0xE7), + GFOF, 8, + Offset (0xE9), + KPCR, 1, + Offset (0xEA), + Offset (0xF0), + PL1T, 16, + PL2T, 16, + TAUT, 8, + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8 +} diff --git a/src/mainboard/system76/whl-u/acpi/gpe.asl b/src/mainboard/system76/whl-u/acpi/gpe.asl new file mode 100644 index 0000000000..d24d53ed57 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/gpe.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// GPP_D9 SCI +Method (_L29, 0, Serialized) { + Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == One) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/system76/whl-u/acpi/hid.asl b/src/mainboard/system76/whl-u/acpi/hid.asl new file mode 100644 index 0000000000..c75fefa6a0 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/hid.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, Zero) + Name (HIDX, Zero) + Name (HRDY, Zero) + + Method (HDEM, 0, Serialized) + { + HBSY = Zero + Return (HIDX) + } + + Method (HDMM, 0, Serialized) + { + Return (Zero) + } + + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + HBSY = One + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = Zero + While (((Local0 < 0xFA) && HBSY)) + { + Sleep (0x04) + Local0++ + } + + If ((HBSY == One)) + { + HBSY = Zero + HIDX = Zero + Return (One) + } + Else + { + Return (Zero) + } + } +} diff --git a/src/mainboard/system76/whl-u/acpi/lid.asl b/src/mainboard/system76/whl-u/acpi/lid.asl new file mode 100644 index 0000000000..0a8688023a --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/lid.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { 0x29 /* GPP_D9 */, 3 }) + + Method (_LID, 0, NotSerialized) { + DEBUG = "LID: _LID" + If (^^PCI0.LPCB.EC0.ECOK) { + Return (^^PCI0.LPCB.EC0.LSTE) + } Else { + Return (One) + } + } + + Method (_PSW, 1, NotSerialized) { + DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0)) + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.LWKE = Arg0 + } + } +} diff --git a/src/mainboard/system76/whl-u/acpi/mainboard.asl b/src/mainboard/system76/whl-u/acpi/mainboard.asl new file mode 100644 index 0000000000..caf6688d6d --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/mainboard.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB) { + #include "ac.asl" + #include "battery.asl" + #include "buttons.asl" + #include "hid.asl" + #include "lid.asl" + #include "s76.asl" +} + +Scope (_GPE) { + #include "gpe.asl" +} diff --git a/src/mainboard/system76/whl-u/acpi/s76.asl b/src/mainboard/system76/whl-u/acpi/s76.asl new file mode 100644 index 0000000000..8f161ae4e9 --- /dev/null +++ b/src/mainboard/system76/whl-u/acpi/s76.asl @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Notifications: +// 0x80 - hardware backlight toggle +// 0x81 - backlight toggle +// 0x82 - backlight down +// 0x83 - backlight up +// 0x84 - backlight color change +Device (S76D) { + Name (_HID, "17761776") + Name (_UID, 0) + + // Get Airplane LED + Method (GAPL, 0, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (^^PCI0.LPCB.EC0.AIRP & 0x40) { + Return (1) + } + } + Return (0) + } + + // Set Airplane LED + Method (SAPL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0) { + ^^PCI0.LPCB.EC0.AIRP |= 0x40 + } Else { + ^^PCI0.LPCB.EC0.AIRP &= 0xBF + } + } + } + +#if CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1325 + // Set KB LED Brightness + Method (SKBL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 6 + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FBF1 = 0 + ^^PCI0.LPCB.EC0.FBF2 = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } + + // Set Keyboard Color + Method (SKBC, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 0x3 + ^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF) + ^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF) + ^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF) + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Return (Arg0) + } Else { + Return (0) + } + } +#elif CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID == 0x1323 + // Get KB LED + Method (GKBL, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = One + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + ^^PCI0.LPCB.EC0.FCMD = Zero + } + Return (Local0) + } + + // Set KB Led + Method (SKBL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = Zero + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } +#else + #error Unknown Mainboard +#endif +} diff --git a/src/mainboard/system76/whl-u/acpi_tables.c b/src/mainboard/system76/whl-u/acpi_tables.c new file mode 100644 index 0000000000..e69de29bb2 diff --git a/src/mainboard/system76/whl-u/board_info.txt b/src/mainboard/system76/whl-u/board_info.txt new file mode 100644 index 0000000000..6ae000b0e6 --- /dev/null +++ b/src/mainboard/system76/whl-u/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: System76 +Board name: whl-u +Category: laptop +Release year: 2019 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/system76/whl-u/cmos.default b/src/mainboard/system76/whl-u/cmos.default new file mode 100644 index 0000000000..b4890abf8d --- /dev/null +++ b/src/mainboard/system76/whl-u/cmos.default @@ -0,0 +1 @@ +DisplayPort_Output=Mini_DisplayPort diff --git a/src/mainboard/system76/whl-u/cmos.layout b/src/mainboard/system76/whl-u/cmos.layout new file mode 100644 index 0000000000..f69185a1f0 --- /dev/null +++ b/src/mainboard/system76/whl-u/cmos.layout @@ -0,0 +1,33 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2019 System76 +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +#start length type id name +0 384 r 0 reserved_memory +384 1 e 1 DisplayPort_Output +984 16 h 0 check_sum + +enumerations + +#ID value text +1 0 Mini_DisplayPort +1 1 USB-C + +checksums + +#checksum start end location +checksum 384 983 984 diff --git a/src/mainboard/system76/whl-u/devicetree.cb b/src/mainboard/system76/whl-u/devicetree.cb new file mode 100644 index 0000000000..a1ca222574 --- /dev/null +++ b/src/mainboard/system76/whl-u/devicetree.cb @@ -0,0 +1,245 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + +# ACPI (soc/intel/cannonlake/acpi.c) + # Enable s0ix + register "s0ix_enable" = "0" + + # PM Timer Enabled + register "PmTimerDisabled" = "0" + + # Disable DPTF + register "dptf_enable" = "0" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "tdp_pl1_override" = "15" + register "tdp_pl2_override" = "25" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + register "VmxEnable" = "1" + #register "enable_c6dram" = "1" + register "DebugConsent" = "DebugConsent_Disabled" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # SATA + register "SataMode" = "Sata_AHCI" + register "SataSalpSupport" = "0" + + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "0" + register "SataPortsEnable[2]" = "1" + register "SataPortsEnable[3]" = "0" + register "SataPortsEnable[4]" = "0" + register "SataPortsEnable[5]" = "0" + register "SataPortsEnable[6]" = "0" + register "SataPortsEnable[7]" = "0" + + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[1]" = "0" + register "SataPortsDevSlp[2]" = "0" + register "SataPortsDevSlp[3]" = "0" + register "SataPortsDevSlp[4]" = "0" + register "SataPortsDevSlp[5]" = "0" + register "SataPortsDevSlp[6]" = "0" + register "SataPortsDevSlp[7]" = "0" + + # Audio + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkDmic0" = "1" + register "PchHdaAudioLinkDmic1" = "1" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkSsp2" = "0" + register "PchHdaAudioLinkSndw1" = "0" + register "PchHdaAudioLinkSndw2" = "0" + register "PchHdaAudioLinkSndw3" = "0" + register "PchHdaAudioLinkSndw4" = "0" + + # USB + register "SsicPortEnable" = "0" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port 1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # 3G / LTE + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port 3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB Board port 4 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Finger print + register "usb2_ports[6]" = "USB2_PORT_MAX(OC_SKIP)" # Camera + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # T17, T18 + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port 1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port 3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB Board port 4 + register "usb3_ports[4]" = "USB3_PORT_EMPTY" # Used by TBT + register "usb3_ports[5]" = "USB3_PORT_EMPTY" # Used by TBT + register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC + + # PCI Express Root port #5 x4, Clock 4 (TBT) + register "PcieRpEnable[4]" = "1" + register "PcieRpLtrEnable[4]" = "1" + register "PcieRpHotPlug[4]" = "1" + register "PcieClkSrcUsage[4]" = "4" + register "PcieClkSrcClkReq[4]" = "4" + + # PCI Express Root port #9 x1, Clock 3 (LAN) + register "PcieRpEnable[8]" = "1" + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + + # PCI Express Root port #10 x1, Clock 2 (WLAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + register "PcieClkSrcUsage[2]" = "9" + register "PcieClkSrcClkReq[2]" = "2" + + # PCI Express Root port #13 x4, Clock 5 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + register "PcieClkSrcUsage[5]" = "12" + register "PcieClkSrcClkReq[5]" = "5" + + # Misc + register "Device4Enable" = "1" + register "HeciEnabled" = "1" + register "AcousticNoiseMitigation" = "1" + #register "dmipwroptimize" = "1" + #register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + + # Serial IRQ Continuous + register "SerialIrqConfigSirqMode" = "1" + +# LPC (soc/intel/cannonlake/lpc.c) + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x84: Decode 0x80 - 0x8F + register "gen1_dec" = "0x000c0081" + # Address 0x88: Decode 0x68 - 0x6F + register "gen2_dec" = "0x00040069" + # Address 0x8C: Decode 0x3320 - 0x332F + register "gen3_dec" = "0x000c3321" + # Address 0x90: Disabled + register "gen4_dec" = "0x00000000" + + # 8254 + register "clock_gate_8254" = "0" + +# PMC (soc/intel/cannonlake/pmc.c) + # Enable deep Sx states + register "deep_s3_enable_ac" = "0" + register "deep_s3_enable_dc" = "0" + register "deep_s5_enable_ac" = "0" + register "deep_s5_enable_dc" = "0" + register "deep_sx_config" = "0" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 12.0 on end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI #2 + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + #chip drivers/intel/wifi + # register "wake" = "PME_B0_EN_BIT" + device pci 14.3 on end # CNVi wifi + #end + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 on end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on end # PCI Express Port 13 + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Interface + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/system76/whl-u/dsdt.asl b/src/mainboard/system76/whl-u/dsdt.asl new file mode 100644 index 0000000000..ccdf5856a5 --- /dev/null +++ b/src/mainboard/system76/whl-u/dsdt.asl @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include + + // global NVS and variables + #include + + // CPU + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + // Chipset specific sleep states + #include + + Scope (\_SB.PCI0.LPCB) { + // PS/2 bus + #include + + // Embedded controller + #include "acpi/ec.asl" + } + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/system76/whl-u/gpio.h b/src/mainboard/system76/whl-u/gpio.h new file mode 100644 index 0000000000..4d480db3f1 --- /dev/null +++ b/src/mainboard/system76/whl-u/gpio.h @@ -0,0 +1,543 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include +#include + +#ifndef __ACPI__ + +#define PAD_CFG_NC(pad) PAD_NC(pad, NONE) + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { +// GPD + // Power Management + // PM_BATLOW# + PAD_CFG_NC(GPD0), + // AC_PRESENT + PAD_CFG_NF(GPD1, NATIVE, DEEP, NF1), + // NC + PAD_CFG_NC(GPD2), + // PWR_BTN# + PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1), + // SUSB#_PCH + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + // SUSC#_PCH + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + // SLP_A# + PAD_CFG_NC(GPD6), + + // GPIO + // NC + PAD_CFG_NC(GPD7), + + // Clock Signals + // SUS_CLK + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + + // Power Management + // GPD9_RTD3 + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPD10), + // NC + PAD_CFG_NC(GPD11), + +// GPP_A + // LPC + // SB_KBCRST# + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), + // LPC_AD0 + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), + // LPC_AD1 + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), + // LPC_AD2 + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), + // LPC_AD3 + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), + // LPC_FRAME# + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + // SERIRQ with pull up + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + // GSPI0 + // TODO - TPM_PIRQ# + PAD_CFG_NC(GPP_A7), + + // LPC + // PM_CLKRUN# with pull-up + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + // PCLK_KBC + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_A10), + + // GSPI1 + // NC + PAD_CFG_NC(GPP_A11), + + // ISH_GP + // PCH_GPP_A12 + PAD_CFG_NC(GPP_A12), + + // Power Management + // SUSWARN# + PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), + + // LPC + // NC + PAD_CFG_NC(GPP_A14), + + // Power Management + // SUS_PWR_ACK + PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), + + // SD + // NC + PAD_CFG_NC(GPP_A16), + // LIGHT_KB_DET# + PAD_CFG_NC(GPP_A17), + + // ISH_GP + // NC + PAD_CFG_NC(GPP_A18), + // SATA_PWR_EN + PAD_CFG_GPO(GPP_A19, 1, DEEP), + // NC + PAD_CFG_NC(GPP_A20), + // NC + PAD_CFG_NC(GPP_A21), + // PS8338B_SW + PAD_CFG_GPO(GPP_A22, 0, DEEP), + // PS8338B_PCH + PAD_CFG_GPO(GPP_A23, 0, DEEP), + +// GPP_B + // Power + // CORE_VID0 + PAD_CFG_NC(GPP_B0), + // CORE_VID1 + PAD_CFG_NC(GPP_B1), + + // Power Management + // CNVI_WAKE# + PAD_CFG_NC(GPP_B2), + + // CPU Misc + // NC + PAD_CFG_NC(GPP_B3), + // NC + PAD_CFG_NC(GPP_B4), + + // Clock Signals + // NC + PAD_CFG_NC(GPP_B5), + // NC + PAD_CFG_NC(GPP_B6), + // WLAN_CLKREQ# + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + // LAN_CLKREQ# + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + // TBT_CLKREQ# + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + // SSD_CLKREQ# + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + + // Power Management + // EXT_PWR_GATE# + PAD_CFG_NC(GPP_B11), + // SLP_S0# + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + // PLT_RST# + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + // SPKR + // PCH_SPKR + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + + // GSPI0 + // NC + PAD_CFG_NC(GPP_B15), + // PCH_GPP_B16 + PAD_CFG_NC(GPP_B16), + // PCH_GPP_B17 + PAD_CFG_NC(GPP_B17), + // PCH_GPP_B18 - strap for disabling no reboot mode + PAD_CFG_NC(GPP_B18), + + // GSPI1 + // NC + PAD_CFG_NC(GPP_B19), + // NC + PAD_CFG_NC(GPP_B20), + // NC + PAD_CFG_NC(GPP_B21), + // PCH_GPP_B22 + PAD_CFG_NC(GPP_B22), + + // SMBUS + // NC + PAD_CFG_NC(GPP_B23), + +// GPP_C + // SMBUS + // SMB_CLK_DDR + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + // SMB_DAT_DDR + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + // PCH_GPP_C2 with pull-up + PAD_CFG_NC(GPP_C2), + // NC + PAD_CFG_NC(GPP_C3), + // NC + PAD_CFG_NC(GPP_C4), + // NC + PAD_CFG_NC(GPP_C5), + // LAN_WAKEUP# + PAD_CFG_NC(GPP_C6), + // NC + PAD_CFG_NC(GPP_C7), + + // UART0 + // NC + PAD_CFG_NC(GPP_C8), + // TBCIO_PLUG_EVENT + _PAD_CFG_STRUCT(GPP_C9, 0x82880100, 0x3000), + // TBT_FRC_PWR + PAD_CFG_GPO(GPP_C10, 1, DEEP), + // NC + PAD_CFG_NC(GPP_C11), + + // UART1 + // GPP_C12_RTD3 + PAD_CFG_GPO(GPP_C12, 1, DEEP), + // SSD_PWR_DN# + PAD_CFG_GPO(GPP_C13, 1, DEEP), + // TBTA_HRESET + PAD_CFG_GPO(GPP_C14, 0, DEEP), + // TBT_PERST_N + PAD_CFG_GPO(GPP_C15, 1, DEEP), + + // I2C + // T_SDA + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + // T_SCL + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_C18), + // SWI + PAD_CFG_NC(GPP_C19), + + // UART2 + // UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_C22), + // NC + PAD_CFG_NC(GPP_C23), + +// GPP_D + // SPI1 + // NC + PAD_CFG_NC(GPP_D0), + // NC + PAD_CFG_NC(GPP_D1), + // NC + PAD_CFG_NC(GPP_D2), + // NC + PAD_CFG_NC(GPP_D3), + + // IMGCLKOUT + // NC + PAD_CFG_NC(GPP_D4), + + // I2C + // NC + PAD_CFG_NC(GPP_D5), + // NC + PAD_CFG_NC(GPP_D6), + // NC + PAD_CFG_NC(GPP_D7), + // SB_BLON + PAD_CFG_GPO(GPP_D8, 1, DEEP), + + // GSPI2 + // SWI# + PAD_CFG_GPI_SCI_LOW(GPP_D9, NONE, DEEP, LEVEL), + // NC + PAD_CFG_NC(GPP_D10), + // RTD3_PCIE_WAKE# + _PAD_CFG_STRUCT(GPP_D11, 0x40880100, 0x3000), + // PCH_GPP_D12 + PAD_CFG_NC(GPP_D12), + + // UART0 + // NC + PAD_CFG_NC(GPP_D13), + // NC + PAD_CFG_NC(GPP_D14), + // NC + PAD_CFG_NC(GPP_D15), + // RTD3_3G_PW R_EN + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + // DMIC + // NC + PAD_CFG_NC(GPP_D17), + // NC + PAD_CFG_NC(GPP_D18), + // GPPC_DMIC_CLK + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + // GPPC_DMIC_DATA + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + + // SPI1 + // TPM_DET# + PAD_CFG_NC(GPP_D21), + // TPM_TCM_Detect + PAD_CFG_NC(GPP_D22), + + // I2S + // NC + PAD_CFG_NC(GPP_D23), + +// GPP_E + // SATA + // PCH_GPP_E0 with pull-up + PAD_CFG_NC(GPP_E0), + // SATA_ODD_PRSNT# + PAD_CFG_NC(GPP_E1), + // SATAGP2 + PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1), + + // CPU Misc + // NC + PAD_CFG_NC(GPP_E3), + + // DEVSLP + // NC + PAD_CFG_NC(GPP_E4), + // NC + PAD_CFG_NC(GPP_E5), + // DEVSLP2 + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), + + // CPU Misc + // NC + PAD_CFG_NC(GPP_E7), + + // SATA + // PCH_SATAHDD_LED# + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + // USB2 + // GP_BSSB_CLK + PAD_CFG_NC(GPP_E9), + // GPP_E10 + PAD_CFG_NC(GPP_E10), + // GPP_E11 + PAD_CFG_NC(GPP_E11), + // USB_OC#78 + PAD_CFG_NC(GPP_E12), + + // Display Signals + // MUX_HPD + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), + // HDMI_HPD + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + // SMI# + _PAD_CFG_STRUCT(GPP_E15, 0x42840100, 0x0), + // SCI# + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), + // EDP_HPD + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + // MDP_CTRLCLK + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + // MDP_CTRLDATA + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + // HDMI_CTRLCLK + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + // HDMI_CTRLDATA + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + // NC + PAD_CFG_NC(GPP_E22), + // NC + PAD_CFG_NC(GPP_E23), + +// GPP_F + // CNVI + // CNVI_GNSS_PA_BLANKING + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + // GPIO + // NC + PAD_CFG_NC(GPP_F1), + // NC + PAD_CFG_NC(GPP_F2), + // NC + PAD_CFG_NC(GPP_F3), + + // CNVI + // CNVI_BRI_DT + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + // CNVI_BRI_RSP + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), + // CNVI_RGI_DT + PAD_CFG_NF(GPP_F6, UP_20K, DEEP, NF1), + // CNVI_RGI_RSP + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + // CNVI_MFUART2_RXD + PAD_CFG_NF(GPP_F8, UP_20K, DEEP, NF1), + // CNVI_MFUART2_TXD + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + + // GPIO + // NC + PAD_CFG_NC(GPP_F10), + + // EMMC + // NC + PAD_CFG_NC(GPP_F11), + // NC + PAD_CFG_NC(GPP_F12), + // NC + PAD_CFG_NC(GPP_F13), + // NC + PAD_CFG_NC(GPP_F14), + // NC + PAD_CFG_NC(GPP_F15), + // NC + PAD_CFG_NC(GPP_F16), + // NC + PAD_CFG_NC(GPP_F17), + // NC + PAD_CFG_NC(GPP_F18), + // NC + PAD_CFG_NC(GPP_F19), + // NC + PAD_CFG_NC(GPP_F20), + // NC + PAD_CFG_NC(GPP_F21), + // NC + PAD_CFG_NC(GPP_F22), + + // A4WP + // A4WP_PRESENT + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + +// GPP_G + // SD + // EDP_DET + PAD_CFG_NC(GPP_G0), + // NC + PAD_CFG_NC(GPP_G1), + // NC + PAD_CFG_NC(GPP_G2), + // ASM1543_I_SEL0 + PAD_CFG_NC(GPP_G3), + // ASM1543_I_SEL1 + PAD_CFG_NC(GPP_G4), + // BOARD_ID + PAD_CFG_NC(GPP_G5), + // NC + PAD_CFG_NC(GPP_G6), + // TBT_Detect + PAD_CFG_NC(GPP_G7), + +// GPP_H + // CNVI + // NC + PAD_CFG_NC(GPP_H0), + // CNVI_RST# + PAD_CFG_NF(GPP_H1, DN_20K, DEEP, NF3), + // CNVI_CLKREQ + PAD_CFG_NF(GPP_H2, DN_20K, DEEP, NF3), + // NC + PAD_CFG_NC(GPP_H3), + + // I2C + // T23 + PAD_CFG_NC(GPP_H4), + // T22 + PAD_CFG_NC(GPP_H5), + // NC + PAD_CFG_NC(GPP_H6), + // NC + PAD_CFG_NC(GPP_H7), + // NC + PAD_CFG_NC(GPP_H8), + // NC + PAD_CFG_NC(GPP_H9), + + // I2C + // NC + PAD_CFG_NC(GPP_H10), + // NC + PAD_CFG_NC(GPP_H11), + + // PCIE + // NC + PAD_CFG_NC(GPP_H12), + // NC + PAD_CFG_NC(GPP_H13), + // G_INT1 + PAD_CFG_NC(GPP_H14), + // NC + PAD_CFG_NC(GPP_H15), + + // Display Signals + // NC + PAD_CFG_NC(GPP_H16), + // NC + PAD_CFG_NC(GPP_H17), + + // CPU Power + // CPU_C10_GATE# + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + // TIMESYNC + // NC + PAD_CFG_NC(GPP_H19), + + // IMGCLKOUT + // NC + PAD_CFG_NC(GPP_H20), + + // GPIO + // GPPC_H21 + PAD_CFG_NC(GPP_H21), + // TBT_RTD3_PWR_EN_R + PAD_CFG_GPO(GPP_H22, 1, DEEP), + // NC, WIGIG_PEWAKE + PAD_CFG_GPO(GPP_H23, 1, DEEP), +}; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { + // UART2 + // UART2_RXD + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + // UART2_TXD + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +}; + +#endif + +#endif diff --git a/src/mainboard/system76/whl-u/ramstage.c b/src/mainboard/system76/whl-u/ramstage.c new file mode 100644 index 0000000000..159b1d3705 --- /dev/null +++ b/src/mainboard/system76/whl-u/ramstage.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include "gpio.h" + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + cnl_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static void mainboard_init(struct device *dev) { + printk(BIOS_INFO, "system76: keyboard init\n"); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static void mainboard_enable(struct device *dev) { + dev->ops->init = mainboard_init; + + // Configure pad for DisplayPort + uint32_t config = 0x44000200; + + uint8_t nvram = 0; + if (get_option(&nvram, "DisplayPort_Output") == CB_SUCCESS) { + if (nvram) { + config |= 1; + } + } + + if (nvram) { + printk(BIOS_INFO, "system76: DisplayPort_Output set to USB-C: 0x%x\n", config); + } else { + printk(BIOS_INFO, "system76: DisplayPort_Output set to Mini_DisplayPort: 0x%x\n", config); + } + + struct pad_config displayport_gpio_table[] = { + /* PS8338B_SW */ + _PAD_CFG_STRUCT(GPP_A22, config, 0x0), + }; + gpio_configure_pads(displayport_gpio_table, ARRAY_SIZE(displayport_gpio_table)); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/system76/whl-u/romstage.c b/src/mainboard/system76/whl-u/romstage.c new file mode 100644 index 0000000000..f34b15c989 --- /dev/null +++ b/src/mainboard/system76/whl-u/romstage.c @@ -0,0 +1,90 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +//TODO: find correct values +static const struct cnl_mb_cfg memcfg = { + /* + * For each channel, there are 3 sets of DQ byte mappings, + * where each set has a package 0 and a package 1 value (package 0 + * represents the first 64-bit lpddr4 chip combination, and package 1 + * represents the second 64-bit lpddr4 chip combination). + * The first three sets are for CLK, CMD, and CTL. + * The fsp package actually expects 6 sets, but the last 3 sets are + * not used in CNL, so we only define the three sets that are used + * and let the meminit_lpddr4() routine take care of clearing the + * unused fields for the caller. + */ + .dq_map[DDR_CH0] = { + {0x0F, 0xF0}, {0x00, 0xF0}, {0x0F, 0xF0}, + //{0x0F, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + .dq_map[DDR_CH1] = { + {0x33, 0xCC}, {0x00, 0xCC}, {0x33, 0xCC}, + //{0x33, 0x00}, {0xFF, 0x00}, {0xFF, 0x00} + }, + + /* + * DQS CPU<>DRAM map Ch0 and Ch1. Each array entry represents a + * mapping of a dq bit on the CPU to the bit it's connected to on + * the memory part. The array index represents the dqs bit number + * on the memory part, and the values in the array represent which + * pin on the CPU that DRAM pin connects to. + */ + .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {1, 0, 2, 3, 4, 5, 6, 7}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* + * Rcomp target values. These will typically be the following + * values for Cannon Lake : { 80, 40, 40, 40, 30 } + */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuraation. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training Enabled */ + .ect = 1, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct spd_info spd = { + .spd_smbus_address[0] = 0xA0, + .spd_smbus_address[2] = 0xA4, + }; + + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg, &spd); +} diff --git a/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c new file mode 100644 index 0000000000..ce9aed8ae5 --- /dev/null +++ b/src/mainboard/system76/whl-u/variants/darp5/hda_verb.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15581325, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581325), + AZALIA_PIN_CFG(0, 0x12, 0x90a60140), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a11050), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41738205), + AZALIA_PIN_CFG(0, 0x1e, 0x02451130), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c new file mode 100644 index 0000000000..200748515f --- /dev/null +++ b/src/mainboard/system76/whl-u/variants/galp3-c/hda_verb.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 System76 + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15581323, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15581323), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x02a11040), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + /* Intel, KabylakeHDMI */ + 0x8086280b, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +#endif