cpu/amd: Reformat code

Most of these changes are suggested by clang-format(13.0-54) tool on
Debian testing.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie4fe0e872e94f38079945970848fefd153ab7cb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>

src/cpu/amd/agesa/family14/fixme.c

@@ -39,7 +39,7 @@ void amd_initcpuio(void)
 	LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
 	MsrReg = (MsrReg >> 8) | 3;
 	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
-	PciData = (UINT32) MsrReg;
+	PciData = (UINT32)MsrReg;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Send all IO (0000-FFFF) to southbridge. */

src/cpu/amd/agesa/family16kb/fixme.c

@@ -16,7 +16,7 @@ void amd_initcpuio(void)
 	AMD_CONFIG_PARAMS StdHeader;
 
 	/* Enable legacy video routing: D18F1xF4 VGA Enable */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
 	PciData = 1;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
@@ -24,29 +24,29 @@ void amd_initcpuio(void)
 	 * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
 	 * set to non-posted regions.
 	 */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
 	PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
 	PciData |= 1 << 7;    /* set NP (non-posted) bit */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
 	PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Map the remaining PCI hole as posted MMIO */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
 	PciData = 0x00FECF00; /* last address before non-posted range */
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 	LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
 	MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
 	PciData = (UINT32)MsrReg;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 
 	/* Send all IO (0000-FFFF) to southbridge. */
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
 	PciData = 0x0000F000;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0);
+	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
 	PciData = 0x00000003;
 	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
 }

src/cpu/amd/mtrr/amd_mtrr.c

@@ -16,8 +16,8 @@ void add_uma_resource_below_tolm(struct device *nb, int idx)
 	uint32_t uma_base = top_of_cacheable;
 	uint32_t uma_size = topmem - top_of_cacheable;
 
-	printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n",
+	printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n", __func__, uma_size,
-			__func__, uma_size, uma_base);
+	       uma_base);
 
 	uma_resource_kb(nb, idx, uma_base / KiB, uma_size / KiB);
 }

src/cpu/amd/pi/00730F01/update_microcode.c

@@ -18,7 +18,7 @@
 #define F16H_MPB_MAX_SIZE 3458
 #define F16H_MPB_DATA_OFFSET 32
 
- /*
+/*
  * STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h
  *	Microcode Patch Block
  *		Microcode Header
@@ -76,8 +76,7 @@ static void apply_microcode_patch(const struct microcode *m)
 
 	wrmsr(MSR_PATCH_LOADER, msr);
 
-	printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n",
+	printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id);
-		m->patch_id);
 
 	msr = rdmsr(IA32_BIOS_SIGN_ID);
 	new_patch_id = msr.lo;
@@ -122,8 +121,7 @@ void amd_update_microcode_from_cbfs(void)
 		return;
 	}
 
-	if (ucode_len > F16H_MPB_MAX_SIZE ||
+	if (ucode_len > F16H_MPB_MAX_SIZE || ucode_len < F16H_MPB_DATA_OFFSET) {
-	    ucode_len < F16H_MPB_DATA_OFFSET) {
 		printk(BIOS_DEBUG, "microcode file invalid. Skipping updates.\n");
 		return;
 	}

src/cpu/amd/smm/smm_init.c

@@ -43,8 +43,7 @@ void smm_init(void)
 
 	enable_cache();
 	/* copy the real SMM handler */
-	memcpy((void *)SMM_BASE, _binary_smm_start,
+	memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start);
-		_binary_smm_end - _binary_smm_start);
 	wbinvd();
 	disable_cache();