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cpu/amd: Reformat code

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Most of these changes are suggested by clang-format(13.0-54) tool on
Debian testing.

Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Change-Id: Ie4fe0e872e94f38079945970848fefd153ab7cb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
This commit is contained in:
Elyes Haouas
2022-05-29 15:44:11 +02:00
committed by Felix Held
parent a3214c050e
commit 287048a500
7 changed files with 55 additions and 58 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/agesa/family14/fixme.c
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@@ -39,7 +39,7 @@ void amd_initcpuio(void)
LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3; MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32) MsrReg; PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ /* Send all IO (0000-FFFF) to southbridge. */

8
src/cpu/amd/agesa/family15tn/fixme.c
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@@ -10,10 +10,10 @@
void amd_initcpuio(void) void amd_initcpuio(void)
{ {
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ /* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);

22
src/cpu/amd/agesa/family16kb/fixme.c
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@@ -10,13 +10,13 @@
void amd_initcpuio(void) void amd_initcpuio(void)
{ {
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ /* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
PciData = 1; PciData = 1;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
@@ -24,29 +24,29 @@ void amd_initcpuio(void)
* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
* set to non-posted regions. * set to non-posted regions.
*/ */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */
PciData |= 1 << 7; /* set NP (non-posted) bit */ PciData |= 1 << 7; /* set NP (non-posted) bit */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */ PciData = (HPET_BASE_ADDRESS >> 8) | 3; /* lowest NP address is HPET at FED00000 */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Map the remaining PCI hole as posted MMIO */ /* Map the remaining PCI hole as posted MMIO */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
PciData = 0x00FECF00; /* last address before non-posted range */ PciData = 0x00FECF00; /* last address before non-posted range */
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
MsrReg = (MsrReg >> 8) | 3; MsrReg = (MsrReg >> 8) | 3;
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
PciData = (UINT32)MsrReg; PciData = (UINT32)MsrReg;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
/* Send all IO (0000-FFFF) to southbridge. */ /* Send all IO (0000-FFFF) to southbridge. */
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
PciData = 0x0000F000; PciData = 0x0000F000;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
PciData = 0x00000003; PciData = 0x00000003;
LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
} }

4
src/cpu/amd/mtrr/amd_mtrr.c
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@@ -16,8 +16,8 @@ void add_uma_resource_below_tolm(struct device *nb, int idx)
uint32_t uma_base = top_of_cacheable; uint32_t uma_base = top_of_cacheable;
uint32_t uma_size = topmem - top_of_cacheable; uint32_t uma_size = topmem - top_of_cacheable;
printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n", printk(BIOS_INFO, "%s: uma size 0x%08x, memory start 0x%08x\n", __func__, uma_size,
__func__, uma_size, uma_base); uma_base);
uma_resource_kb(nb, idx, uma_base / KiB, uma_size / KiB); uma_resource_kb(nb, idx, uma_base / KiB, uma_size / KiB);
} }

8
src/cpu/amd/pi/00730F01/fixme.c
View File

@@ -11,10 +11,10 @@
void amd_initcpuio(void) void amd_initcpuio(void)
{ {
UINT64 MsrReg; UINT64 MsrReg;
UINT32 PciData; UINT32 PciData;
PCI_ADDR PciAddress; PCI_ADDR PciAddress;
AMD_CONFIG_PARAMS StdHeader; AMD_CONFIG_PARAMS StdHeader;
/* Enable legacy video routing: D18F1xF4 VGA Enable */ /* Enable legacy video routing: D18F1xF4 VGA Enable */
PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);

66
src/cpu/amd/pi/00730F01/update_microcode.c
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@@ -18,33 +18,33 @@
#define F16H_MPB_MAX_SIZE 3458 #define F16H_MPB_MAX_SIZE 3458
#define F16H_MPB_DATA_OFFSET 32 #define F16H_MPB_DATA_OFFSET 32
/* /*
* STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h * STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h
* Microcode Patch Block * Microcode Patch Block
* Microcode Header * Microcode Header
* Microcode "Blob" * Microcode "Blob"
* ... * ...
* ... * ...
* (end of file) * (end of file)
* *
* *
* MICROCODE HEADER (offset 0 bytes from start of file) * MICROCODE HEADER (offset 0 bytes from start of file)
* Total size = 32 bytes * Total size = 32 bytes
* [0:3] Date code (32 bits) * [0:3] Date code (32 bits)
* [4:7] Patch level (32 bits) * [4:7] Patch level (32 bits)
* [8:9] Microcode patch data ID (16 bits) * [8:9] Microcode patch data ID (16 bits)
* [10:15] Reserved (48 bits) * [10:15] Reserved (48 bits)
* [16:19] Chipset 1 device ID (32 bits) * [16:19] Chipset 1 device ID (32 bits)
* [20:23] Chipset 2 device ID (32 bits) * [20:23] Chipset 2 device ID (32 bits)
* [24:25] Processor Revisions ID (16 bits) * [24:25] Processor Revisions ID (16 bits)
* [26] Chipset 1 revision ID (8 bits) * [26] Chipset 1 revision ID (8 bits)
* [27] Chipset 2 revision ID (8 bits) * [27] Chipset 2 revision ID (8 bits)
* [28:31] Reserved (32 bits) * [28:31] Reserved (32 bits)
* *
* MICROCODE BLOB (offset += 32) * MICROCODE BLOB (offset += 32)
* Total size = m bytes * Total size = m bytes
* *
*/ */
struct microcode { struct microcode {
uint32_t date_code; uint32_t date_code;
@@ -76,18 +76,17 @@ static void apply_microcode_patch(const struct microcode *m)
wrmsr(MSR_PATCH_LOADER, msr); wrmsr(MSR_PATCH_LOADER, msr);
printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id);
m->patch_id);
msr = rdmsr(IA32_BIOS_SIGN_ID); msr = rdmsr(IA32_BIOS_SIGN_ID);
new_patch_id = msr.lo; new_patch_id = msr.lo;
if (new_patch_id == m->patch_id) if (new_patch_id == m->patch_id)
printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n", printk(BIOS_INFO, "microcode: being updated to patch id = 0x%08x succeeded\n",
new_patch_id); new_patch_id);
else else
printk(BIOS_ERR, "microcode: being updated to patch id = 0x%08x failed\n", printk(BIOS_ERR, "microcode: being updated to patch id = 0x%08x failed\n",
new_patch_id); new_patch_id);
} }
static uint16_t get_equivalent_processor_rev_id(void) static uint16_t get_equivalent_processor_rev_id(void)
@@ -98,7 +97,7 @@ static uint16_t get_equivalent_processor_rev_id(void)
} }
static void amd_update_microcode(const void *ucode, size_t ucode_len, static void amd_update_microcode(const void *ucode, size_t ucode_len,
uint16_t equivalent_processor_rev_id) uint16_t equivalent_processor_rev_id)
{ {
const struct microcode *m; const struct microcode *m;
const uint8_t *c = ucode; const uint8_t *c = ucode;
@@ -122,8 +121,7 @@ void amd_update_microcode_from_cbfs(void)
return; return;
} }
if (ucode_len > F16H_MPB_MAX_SIZE || if (ucode_len > F16H_MPB_MAX_SIZE || ucode_len < F16H_MPB_DATA_OFFSET) {
ucode_len < F16H_MPB_DATA_OFFSET) {
printk(BIOS_DEBUG, "microcode file invalid. Skipping updates.\n"); printk(BIOS_DEBUG, "microcode file invalid. Skipping updates.\n");
return; return;
} }

3
src/cpu/amd/smm/smm_init.c
View File

@@ -43,8 +43,7 @@ void smm_init(void)
enable_cache(); enable_cache();
/* copy the real SMM handler */ /* copy the real SMM handler */
memcpy((void *)SMM_BASE, _binary_smm_start, memcpy((void *)SMM_BASE, _binary_smm_start, _binary_smm_end - _binary_smm_start);
_binary_smm_end - _binary_smm_start);
wbinvd(); wbinvd();
disable_cache(); disable_cache();