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soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage

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List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API

Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik
2020-09-27 11:30:58 +05:30
parent 95bab4077e
commit 2871e0e78c
35 changed files with 3191 additions and 18 deletions
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20
src/soc/intel/alderlake/chip.h
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@@ -11,6 +11,8 @@
#include <soc/pch.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>
#include <soc/serialio.h>
#include <soc/usb.h>
#include <stdint.h>
#define MAX_HD_AUDIO_DMIC_LINKS 2
@@ -177,7 +179,6 @@ struct soc_intel_alderlake_config {
uint8_t SkipExtGfxScan;
uint32_t GraphicsConfigPtr;
uint8_t Device4Enable;
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
@@ -239,16 +240,25 @@ struct soc_intel_alderlake_config {
/* Enable Pch iSCLK */
uint8_t pch_isclk;
/* CNVi */
uint8_t CnviMode;
uint8_t CnviBtCore;
/* CNVi BT Audio Offload: Enable/Disable BT Audio Offload. */
enum {
FORCE_DISABLE,
FORCE_ENABLE,
} CnviBtAudioOffload;
/*
* IOM Port Config
* If a port orientation needs to be controlled by the SOC this setting must be
* updated to reflect the correct GPIOs being used for the SOC port flipping.
* There are 4 ports each with a pair of GPIOs for Pull Up and Pull Down
* 0,1 are pull up and pull down for port 0
* 2,3 are pull up and pull down for port 1
* 4,5 are pull up and pull down for port 2
* 6,7 are pull up and pull down for port 3
* values to be programmed correspond to the GPIO family and offsets
*/
uint32_t IomTypeCPortPadCfg[8];
/*
* SOC Aux orientation override:
* This is a bitfield that corresponds to up to 4 TCSS ports on ADL.