soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage
List of changes: 1. Add required SoC programming till ramstage 2. Include only required headers into include/soc 3. Add CPU, PCH and SA EDS document number and chapter number 4. Fill required FSP-S UPD to call FSP-S API Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik
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src/soc/intel/alderlake/cpu.c
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src/soc/intel/alderlake/cpu.c
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* This file is created based on Intel Alder Lake Processor CPU Datasheet
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* Document number: 619501
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* Chapter number: 14
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*/
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#include <arch/cpu.h>
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#include <console/console.h>
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#include <device/pci.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/mp.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/smm_reloc.h>
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#include <cpu/intel/turbo.h>
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#include <fsp/api.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/mp_init.h>
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#include <intelblocks/msr.h>
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#include <romstage_handoff.h>
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#include <soc/cpu.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/pm.h>
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#include <soc/soc_chip.h>
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static void soc_fsp_load(void)
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{
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fsps_load(romstage_handoff_is_resume());
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}
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static void configure_isst(void)
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{
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config_t *conf = config_of_soc();
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msr_t msr;
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if (conf->speed_shift_enable) {
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/*
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* Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP
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* is supported or not. coreboot needs to configure MSR 0x1AA
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* which is then reflected in the CPUID register.
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*/
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msr = rdmsr(MSR_MISC_PWR_MGMT);
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msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */
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msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */
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msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */
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wrmsr(MSR_MISC_PWR_MGMT, msr);
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} else {
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msr = rdmsr(MSR_MISC_PWR_MGMT);
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msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */
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msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */
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msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */
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wrmsr(MSR_MISC_PWR_MGMT, msr);
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}
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}
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static void configure_misc(void)
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{
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msr_t msr;
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config_t *conf = config_of_soc();
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msr = rdmsr(IA32_MISC_ENABLE);
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msr.lo |= (1 << 0); /* Fast String enable */
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msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
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wrmsr(IA32_MISC_ENABLE, msr);
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/* Set EIST status */
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cpu_set_eist(conf->eist_enable);
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/* Disable Thermal interrupts */
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msr.lo = 0;
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msr.hi = 0;
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wrmsr(IA32_THERM_INTERRUPT, msr);
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/* Enable package critical interrupt only */
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msr.lo = 1 << 4;
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msr.hi = 0;
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wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
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/* Enable PROCHOT */
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msr = rdmsr(MSR_POWER_CTL);
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msr.lo |= (1 << 0); /* Enable Bi-directional PROCHOT as an input*/
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msr.lo |= (1 << 23); /* Lock it */
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wrmsr(MSR_POWER_CTL, msr);
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}
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static void enable_lapic_tpr(void)
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{
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msr_t msr;
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msr = rdmsr(MSR_PIC_MSG_CONTROL);
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msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
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wrmsr(MSR_PIC_MSG_CONTROL, msr);
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}
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static void configure_dca_cap(void)
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{
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uint32_t feature_flag;
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msr_t msr;
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/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
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feature_flag = cpu_get_feature_flags_ecx();
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if (feature_flag & CPUID_DCA) {
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msr = rdmsr(IA32_PLATFORM_DCA_CAP);
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msr.lo |= 1;
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wrmsr(IA32_PLATFORM_DCA_CAP, msr);
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}
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}
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static void enable_pm_timer_emulation(void)
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{
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/* ACPI PM timer emulation */
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msr_t msr;
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/*
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* The derived frequency is calculated as follows:
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* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
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* Back solve the multiplier so the 3.579545MHz ACPI timer
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* frequency is used.
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*/
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msr.hi = (3579545ULL << 32) / CTC_FREQ;
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/* Set PM1 timer IO port and enable */
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msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
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EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
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wrmsr(MSR_EMULATE_PM_TIMER, msr);
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}
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static void set_energy_perf_bias(u8 policy)
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{
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msr_t msr;
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int ecx;
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/* Determine if energy efficient policy is supported. */
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ecx = cpuid_ecx(0x6);
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if (!(ecx & (1 << 3)))
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return;
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/* Energy Policy is bits 3:0 */
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msr = rdmsr(IA32_ENERGY_PERF_BIAS);
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msr.lo &= ~0xf;
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msr.lo |= policy & 0xf;
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wrmsr(IA32_ENERGY_PERF_BIAS, msr);
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}
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/* All CPUs including BSP will run the following function. */
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void soc_core_init(struct device *cpu)
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{
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/* Clear out pending MCEs */
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/* TODO(adurbin): This should only be done on a cold boot. Also, some
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* of these banks are core vs package scope. For now every CPU clears
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* every bank. */
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mca_configure();
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/* Enable the local CPU apics */
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enable_lapic_tpr();
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setup_lapic();
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/* Configure Enhanced SpeedStep and Thermal Sensors */
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configure_misc();
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/* Configure Intel Speed Shift */
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configure_isst();
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/* Enable PM timer emulation */
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enable_pm_timer_emulation();
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/* Enable Direct Cache Access */
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configure_dca_cap();
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/* Set energy policy */
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set_energy_perf_bias(ENERGY_POLICY_NORMAL);
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/* Enable Turbo */
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enable_turbo();
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}
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static void per_cpu_smm_trigger(void)
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{
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/* Relocate the SMM handler. */
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smm_relocate();
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}
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static void post_mp_init(void)
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{
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/* Set Max Ratio */
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cpu_set_max_ratio();
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/*
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* Now that all APs have been relocated as well as the BSP let SMIs
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* start flowing.
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*/
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global_smi_enable();
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}
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static const struct mp_ops mp_ops = {
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/*
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* Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP,
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* that are set prior to ramstage.
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* Real MTRRs programming are being done after resource allocation.
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*/
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.pre_mp_init = soc_fsp_load,
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.get_cpu_count = get_cpu_count,
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.get_smm_info = smm_info,
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.get_microcode_info = get_microcode_info,
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.pre_mp_smm_init = smm_initialize,
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.per_cpu_smm_trigger = per_cpu_smm_trigger,
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.relocation_handler = smm_relocation_handler,
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.post_mp_init = post_mp_init,
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};
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void soc_init_cpus(struct bus *cpu_bus)
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{
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if (mp_init_with_smm(cpu_bus, &mp_ops))
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printk(BIOS_ERR, "MP initialization failure.\n");
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/* Thermal throttle activation offset */
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configure_tcc_thermal_target();
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}
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