soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage
2. Include only required headers into include/soc
3. Add CPU, PCH and SA EDS document number and chapter number
4. Fill required FSP-S UPD to call FSP-S API

Change-Id: I3394f585d66b14ece67cde9e45ffa1177406f35f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/soc/intel/alderlake/systemagent.c

@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * This file is created based on Intel Alder Lake Processor SA Datasheet
+ * Document number: 619503
+ * Chapter number: 3
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <intelblocks/systemagent.h>
+#include <soc/iomap.h>
+#include <soc/systemagent.h>
+
+/*
+ * SoC implementation
+ *
+ * Add all known fixed memory ranges for Host Controller/Memory
+ * controller.
+ */
+void soc_add_fixed_mmio_resources(struct device *dev, int *index)
+{
+	static const struct sa_mmio_descriptor soc_fixed_resources[] = {
+		{ PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS, CONFIG_SA_PCIEX_LENGTH,
+				"PCIEXBAR" },
+		{ MCHBAR, MCH_BASE_ADDRESS, MCH_BASE_SIZE, "MCHBAR" },
+		{ DMIBAR, DMI_BASE_ADDRESS, DMI_BASE_SIZE, "DMIBAR" },
+		{ EPBAR, EP_BASE_ADDRESS, EP_BASE_SIZE, "EPBAR" },
+		{ REGBAR, REG_BASE_ADDRESS, REG_BASE_SIZE, "REGBAR" },
+		{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
+	};
+
+	sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
+			ARRAY_SIZE(soc_fixed_resources));
+
+	/* Add Vt-d resources if VT-d is enabled */
+	if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE))
+		return;
+
+	sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
+			ARRAY_SIZE(soc_vtd_resources));
+}
+
+/*
+ * SoC implementation
+ *
+ * Perform System Agent Initialization during Ramstage phase.
+ */
+void soc_systemagent_init(struct device *dev)
+{
+	/* Enable Power Aware Interrupt Routing */
+	enable_power_aware_intr();
+
+	/* Enable BIOS Reset CPL */
+	enable_bios_reset_cpl();
+	/* TODO: Add set_power_limits() */
+}
+
+uint32_t soc_systemagent_max_chan_capacity_mib(u8 capid0_a_ddrsz)
+{
+	switch (capid0_a_ddrsz) {
+	case 1:
+		return 8192;
+	case 2:
+		return 4096;
+	case 3:
+		return 2048;
+	default:
+		return 65536;
+	}
+}