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acpi: Replace EC_ENABLE_AMD_DPTC_SUPPORT with Kconfig value

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Compile-time support of DPTC is controlled by
EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes
EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value
SOC_AMD_COMMON_BLOCK_ACPI_DPTC.

Each variant's run-time support of DPTC continues to be controlled by
the variant's overridetree.cb "dptc_enable" value.

BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Boot skyrim

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Tim Van Patten
2022-08-29 11:36:35 -06:00
committed by Martin Roth
parent 9e86b71e79
commit 2873fd2770
4 changed files with 11 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/ec/google/chromeec/acpi/ec.asl
View File

@@ -17,7 +17,7 @@
External (\_SB.DPTF.TCHG, DeviceObj) External (\_SB.DPTF.TCHG, DeviceObj)
#endif #endif
/* Enable DPTC interface with AMD ALIB */ /* Enable DPTC interface with AMD ALIB */
#ifdef EC_ENABLE_AMD_DPTC_SUPPORT #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
External(\_SB.DPTC, MethodObj) External(\_SB.DPTC, MethodObj)
#endif #endif
@@ -177,7 +177,7 @@ Device (EC0)
// Initialize LID switch state // Initialize LID switch state
Store (LIDS, \LIDS) Store (LIDS, \LIDS)
#ifdef EC_ENABLE_AMD_DPTC_SUPPORT #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
/* /*
* Per the device mode (clamshell or tablet) to initialize * Per the device mode (clamshell or tablet) to initialize
* the thermal setting on OS startup. * the thermal setting on OS startup.
@@ -435,7 +435,7 @@ Device (EC0)
#ifdef EC_ENABLE_TBMC_DEVICE #ifdef EC_ENABLE_TBMC_DEVICE
Notify (TBMC, 0x80) Notify (TBMC, 0x80)
#endif #endif
#ifdef EC_ENABLE_AMD_DPTC_SUPPORT #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)
If (CondRefOf (\_SB.DPTC)) { If (CondRefOf (\_SB.DPTC)) {
\_SB.DPTC() \_SB.DPTC()
} }

3
src/mainboard/google/zork/variants/morphius/include/variant/ec.h
View File

@@ -6,9 +6,6 @@
#define SIO_EC_ENABLE_PS2M #define SIO_EC_ENABLE_PS2M
#define SIO_EC_PS2M_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {12} #define SIO_EC_PS2M_IRQ Interrupt (ResourceConsumer, Level, ActiveLow, Shared) {12}
/* Enable DPTC support */
#define EC_ENABLE_AMD_DPTC_SUPPORT
#undef MAINBOARD_EC_S3_WAKE_EVENTS #undef MAINBOARD_EC_S3_WAKE_EVENTS
#undef MAINBOARD_EC_S3_DEVICE_EVENTS #undef MAINBOARD_EC_S3_DEVICE_EVENTS
#define MAINBOARD_EC_S3_WAKE_EVENTS \ #define MAINBOARD_EC_S3_WAKE_EVENTS \

7
src/soc/amd/common/block/acpi/Kconfig
View File

@@ -8,6 +8,13 @@ config SOC_AMD_COMMON_BLOCK_ACPI
config SOC_AMD_COMMON_BLOCK_ACPI_ALIB config SOC_AMD_COMMON_BLOCK_ACPI_ALIB
bool bool
config SOC_AMD_COMMON_BLOCK_ACPI_DPTC
bool
depends on SOC_AMD_COMMON_BLOCK_ACPI_ALIB
help
Selected by mainboards that implement support for ALIB
to enable DPTC.
config SOC_AMD_COMMON_BLOCK_ACPI_CPPC config SOC_AMD_COMMON_BLOCK_ACPI_CPPC
bool bool

1
src/soc/amd/picasso/Kconfig
View File

@@ -37,6 +37,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPI
select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO
select SOC_AMD_COMMON_BLOCK_ACPI_ALIB select SOC_AMD_COMMON_BLOCK_ACPI_ALIB
select SOC_AMD_COMMON_BLOCK_ACPI_DPTC
select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_GPIO
select SOC_AMD_COMMON_BLOCK_ACPI_IVRS select SOC_AMD_COMMON_BLOCK_ACPI_IVRS
select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_AOAC