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nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK

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A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
  against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
  existing bootblock_mainboard_early_init().

Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
2019-10-10 15:50:04 +02:00
committed by Nico Huber
parent b9c9cd75e7
commit 2882253237
16 changed files with 94 additions and 152 deletions
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4
src/cpu/intel/model_2065x/Kconfig
View File

@@ -23,10 +23,6 @@ config CPU_SPECIFIC_OPTIONS
select NO_FIXED_XIP_ROM_SIZE
select PARALLEL_MP
config BOOTBLOCK_CPU_INIT
string
default "cpu/intel/model_2065x/bootblock.c"
config SMM_TSEG_SIZE
hex
default 0x800000

5
src/cpu/intel/model_2065x/Makefile.inc
View File

@@ -15,7 +15,10 @@ smm-y += finalize.c
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
bootblock-y += ../car/non-evict/cache_as_ram.S
bootblock-y += ../car/bootblock.c
bootblock-y += ../../x86/early_reset.S
postcar-y += ../car/non-evict/exit_car.S
romstage-y += ../car/romstage.c

64
src/cpu/intel/model_2065x/bootblock.c
View File

@@ -1,64 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <arch/cpu.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <arch/io.h>
#include <halt.h>
#include <cpu/intel/microcode/microcode.c>
#if CONFIG(SOUTHBRIDGE_INTEL_IBEXPEAK)
#include <southbridge/intel/ibexpeak/pch.h>
#include "model_2065x.h"
#else
#error "CPU must be paired with Intel Ibex Peak southbridge"
#endif
static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size,
unsigned int type)
{
/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
/* FIXME: It only support 4G less range */
msr_t basem, maskm;
basem.lo = base | type;
basem.hi = 0;
wrmsr(MTRR_PHYS_BASE(reg), basem);
maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID;
maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
wrmsr(MTRR_PHYS_MASK(reg), maskm);
}
static void enable_rom_caching(void)
{
msr_t msr;
disable_cache();
set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
enable_cache();
/* Enable Variable MTRRs */
msr.hi = 0x00000000;
msr.lo = 0x00000800;
wrmsr(MTRR_DEF_TYPE_MSR, msr);
}
static void bootblock_cpu_init(void)
{
enable_rom_caching();
intel_update_microcode_from_cbfs();
}