nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK
A few notable changes: - Microcode init is done in assembly during the CAR init. - The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size against which the romstage stack guards protected. - The romstage mainboard_lpc_init() hook is removed in favor of the existing bootblock_mainboard_early_init(). Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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Nico Huber
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@@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_NEHALEM
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select INTEL_GMA_ACPI
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select CACHE_MRC_SETTINGS
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select HAVE_DEBUG_RAM_SETUP
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select C_ENVIRONMENT_BOOTBLOCK
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if NORTHBRIDGE_INTEL_NEHALEM
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@@ -48,9 +49,12 @@ config DCACHE_RAM_SIZE
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hex
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default 0x10000
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config BOOTBLOCK_NORTHBRIDGE_INIT
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string
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default "northbridge/intel/nehalem/bootblock.c"
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config DCACHE_BSP_STACK_SIZE
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hex
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default 0x2000
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help
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The amount of anticipated stack usage in CAR by bootblock and
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other stages.
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config MRC_CACHE_SIZE
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hex
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@@ -15,6 +15,8 @@
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ifeq ($(CONFIG_NORTHBRIDGE_INTEL_NEHALEM),y)
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bootblock-y += bootblock.c
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ramstage-y += memmap.c
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ramstage-y += northbridge.c
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ramstage-y += smi.c
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@@ -12,8 +12,9 @@
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*/
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#include <device/pci_ops.h>
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#include <cpu/intel/car/bootblock.h>
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static void bootblock_northbridge_init(void)
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void bootblock_early_northbridge_init(void)
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{
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pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, CONFIG_MMCONF_BASE_ADDRESS | 1);
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pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0);
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@@ -45,11 +45,6 @@ void mainboard_romstage_entry(void)
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/* TODO, make this configurable */
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nehalem_early_initialization(NEHALEM_MOBILE);
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pch_pre_console_init();
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/* Initialize console device(s) */
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console_init();
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early_pch_init();
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/* Read PM1_CNT, DON'T CLEAR IT or raminit will fail! */
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