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nb/intel/nehalem: Move to C_ENVIRONMENT_BOOTBLOCK

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A few notable changes:
- Microcode init is done in assembly during the CAR init.
- The DCACHE_BSP_STACK_SIZE is set to 0x2000, which is the same size
  against which the romstage stack guards protected.
- The romstage mainboard_lpc_init() hook is removed in favor of the
  existing bootblock_mainboard_early_init().

Change-Id: Iccd7ceaa35db49e170bfb901bbff1c1a11223c63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Arthur Heymans
2019-10-10 15:50:04 +02:00
committed by Nico Huber
parent b9c9cd75e7
commit 2882253237
16 changed files with 94 additions and 152 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/southbridge/intel/ibexpeak/Kconfig
View File

@@ -51,10 +51,6 @@ config DRAM_RESET_GATE_GPIO
int
default 60
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/ibexpeak/bootblock.c"
config SERIRQ_CONTINUOUS_MODE
bool
default n

2
src/southbridge/intel/ibexpeak/Makefile.inc
View File

@@ -15,6 +15,8 @@
ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_IBEXPEAK),y)
bootblock-y += bootblock.c
ramstage-y += pch.c
ramstage-y += azalia.c
ramstage-y += lpc.c

62
src/southbridge/intel/ibexpeak/bootblock.c
View File

@@ -14,7 +14,9 @@
*/
#include <device/pci_ops.h>
#include <cpu/intel/car/bootblock.h>
#include "pch.h"
#include "chip.h"
/*
* Enable Prefetching and Caching.
@@ -32,18 +34,7 @@ static void enable_spi_prefetch(void)
static void enable_port80_on_lpc(void)
{
pci_devfn_t dev = PCH_LPC_DEV;
/* Enable port 80 POST on LPC */
pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
#if 0
RCBA32(GCS) &= (~0x04);
#else
volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
u32 reg32 = *gcs;
reg32 = reg32 & ~0x04;
*gcs = reg32;
#endif
RCBA32(GCS) &= ~4;
}
static void set_spi_speed(void)
@@ -66,12 +57,57 @@ static void set_spi_speed(void)
RCBA8(0x3893) = ssfc;
}
static void bootblock_southbridge_init(void)
static void early_lpc_init(void)
{
const struct device *dev = pcidev_on_root(0x1f, 0);
const struct southbridge_intel_ibexpeak_config *config = NULL;
/* Add some default decode ranges:
- 0x2e/2f, 0x4e/0x4f
- EC/Mouse/KBC 60/64, 62/66
- 0x3f8 COMA
If more are needed, update in mainboard_lpc_init hook
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
/* Clear PWR_FLR */
pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
(pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
pci_write_config32(PCH_LPC_DEV, ETR3,
pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
/* Set up generic decode ranges */
if (!dev)
return;
if (dev->chip_info)
config = dev->chip_info;
if (!config)
return;
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
}
void bootblock_early_southbridge_init(void)
{
enable_spi_prefetch();
/* Enable RCBA */
pci_devfn_t lpc_dev = PCI_DEV(0, 0x1f, 0);
pci_write_config32(lpc_dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1);
enable_port80_on_lpc();
set_spi_speed();
/* Enable upper 128bytes of CMOS */
RCBA32(RC) = (1 << 2);
early_lpc_init();
}

45
src/southbridge/intel/ibexpeak/early_pch.c
View File

@@ -22,45 +22,6 @@
#include <southbridge/intel/ibexpeak/pch.h>
#include <southbridge/intel/common/gpio.h>
#include "chip.h"
static void early_lpc_init(void)
{
const struct device *dev = pcidev_on_root(0x1f, 0);
const struct southbridge_intel_ibexpeak_config *config = NULL;
/* Add some default decode ranges:
- 0x2e/2f, 0x4e/0x4f
- EC/Mouse/KBC 60/64, 62/66
- 0x3f8 COMA
If more are needed, update in mainboard_lpc_init hook
*/
pci_write_config16(PCH_LPC_DEV, LPC_EN,
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
COMA_LPC_EN);
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
/* Clear PWR_FLR */
pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3,
(pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1);
pci_write_config32(PCH_LPC_DEV, ETR3,
pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR);
/* Set up generic decode ranges */
if (!dev)
return;
if (dev->chip_info)
config = dev->chip_info;
if (!config)
return;
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
}
static void early_gpio_init(void)
{
pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
@@ -80,12 +41,6 @@ static void pch_default_disable(void)
RCBA32(FD2) = 1;
}
void pch_pre_console_init(void)
{
early_lpc_init();
mainboard_lpc_init();
}
void early_pch_init(void)
{
early_gpio_init();

2
src/southbridge/intel/ibexpeak/pch.h
View File

@@ -62,13 +62,11 @@ int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf);
int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf);
#endif
void pch_pre_console_init(void);
void early_pch_init(void);
void early_thermal_init(void);
void southbridge_configure_default_intmap(void);
void pch_setup_cir(int chipset_type);
void mainboard_lpc_init(void);
enum current_lookup_idx {
IF1_F57 = 0,