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soc/intel: Use config_of_path(SA_DEVFN_ROOT)

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We do not want to disguise somewhat complex function
calls as simple macros.

Change-Id: I53324603c9ece1334c6e09d51338084166f7a585
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Guckian
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2019-07-12 13:10:19 +03:00
parent 4323d26247
commit 28dc7dce83
34 changed files with 102 additions and 215 deletions
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17
src/soc/intel/apollolake/acpi.c
View File

@@ -90,7 +90,7 @@ acpi_cstate_t *soc_get_cstate_map(size_t *entries)
void acpi_create_gnvs(struct global_nvs_t *gnvs)
{
struct soc_intel_apollolake_config *cfg;
struct device *dev = SA_DEV_ROOT;
cfg = config_of_path(SA_DEVFN_ROOT);
/* Clear out GNVS. */
memset(gnvs, 0, sizeof(*gnvs));
@@ -110,12 +110,6 @@ void acpi_create_gnvs(struct global_nvs_t *gnvs)
/* CPU core count */
gnvs->pcnt = dev_count_cpu();
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
cfg = dev->chip_info;
/* Enable DPTF based on mainboard configuration */
gnvs->dpte = cfg->dptf_enable;
@@ -158,7 +152,7 @@ int soc_madt_sci_irq_polarity(int sci)
void soc_fill_fadt(acpi_fadt_t *fadt)
{
const struct soc_intel_apollolake_config *cfg;
struct device *dev = SA_DEV_ROOT;
cfg = config_of_path(SA_DEVFN_ROOT);
fadt->pm_tmr_blk = ACPI_BASE_ADDRESS + PM1_TMR;
@@ -174,13 +168,8 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
fadt->x_pm_tmr_blk.addrl = ACPI_BASE_ADDRESS + PM1_TMR;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
cfg = dev->chip_info;
if(cfg->lpss_s0ix_enable)
if (cfg->lpss_s0ix_enable)
fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
}

31
src/soc/intel/apollolake/chip.c
View File

@@ -295,24 +295,18 @@ static void pcie_override_devicetree_after_silicon_init(void)
static void set_power_limits(void)
{
static struct soc_intel_apollolake_config *cfg;
struct device *dev = SA_DEV_ROOT;
msr_t rapl_msr_reg, limit;
uint32_t power_unit;
uint32_t tdp, min_power, max_power;
uint32_t pl2_val;
cfg = config_of_path(SA_DEVFN_ROOT);
if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
printk(BIOS_INFO, "Skip the RAPL settings.\n");
return;
}
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
cfg = dev->chip_info;
/* Get units */
rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT);
power_unit = 1 << (rapl_msr_reg.lo & 0xf);
@@ -368,15 +362,9 @@ static void set_power_limits(void)
static void set_sci_irq(void)
{
static struct soc_intel_apollolake_config *cfg;
struct device *dev = SA_DEV_ROOT;
uint32_t scis;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
cfg = dev->chip_info;
cfg = config_of_path(SA_DEVFN_ROOT);
/* Change only if a device tree entry exists. */
if (cfg->sci_irq) {
@@ -550,7 +538,7 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
static void parse_devicetree(FSP_S_CONFIG *silconfig)
{
struct device *dev = SA_DEV_ROOT;
struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
if (!dev) {
printk(BIOS_ERR, "Could not find root device\n");
@@ -679,21 +667,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
{
FSP_S_CONFIG *silconfig = &silupd->FspsConfig;
static struct soc_intel_apollolake_config *cfg;
struct device *dev;
/* Load VBT before devicetree-specific config. */
silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get();
struct device *dev = SA_DEV_ROOT;
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
dev = pcidev_path_on_root(SA_DEVFN_ROOT);
cfg = config_of(dev);
mainboard_devtree_update(dev);
cfg = dev->chip_info;
/* Parse device tree and disable unused device*/
parse_devicetree(silconfig);

9
src/soc/intel/apollolake/cpu.c
View File

@@ -295,14 +295,7 @@ void cpu_lock_sgx_memory(void)
int soc_fill_sgx_param(struct sgx_param *sgx_param)
{
struct device *dev = SA_DEV_ROOT;
assert(dev != NULL);
config_t *conf = dev->chip_info;
if (!conf) {
printk(BIOS_ERR, "Failed to get chip_info for SGX param\n");
return -1;
}
config_t *conf = config_of_path(SA_DEVFN_ROOT);
sgx_param->enable = conf->sgx_enable;
return 0;

8
src/soc/intel/apollolake/pmutil.c
View File

@@ -148,13 +148,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
{
DEVTREE_CONST struct soc_intel_apollolake_config *config;
/* Look up the device in devicetree */
DEVTREE_CONST struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
}
config = dev->chip_info;
config = config_of_path(SA_DEVFN_ROOT);
/* Assign to out variable */
*dw0 = config->gpe0_dw1;

6
src/soc/intel/apollolake/pnpconfig.c
View File

@@ -37,8 +37,10 @@ static void pnp_settings(void *unused)
int index;
size_t arrsize;
const struct pnpconfig *pnpconfigarr;
struct device *dev = SA_DEV_ROOT;
struct soc_intel_apollolake_config *config = dev->chip_info;
struct soc_intel_apollolake_config *config;
config = config_of_path(SA_DEVFN_ROOT);
switch (config->pnp_settings) {
case PNP_PERF:
pnpconfigarr = perf;

11
src/soc/intel/apollolake/romstage.c
View File

@@ -100,17 +100,8 @@ static void soc_early_romstage_init(void)
/* Thermal throttle activation offset */
static void configure_thermal_target(void)
{
const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
if (!dev) {
printk(BIOS_ERR, "Could not find SOC devicetree config\n");
return;
}
const config_t *conf = dev->chip_info;
if (!dev->chip_info) {
printk(BIOS_ERR, "Could not find chip info\n");
return;
}
msr_t msr;
const config_t *conf = config_of_path(SA_DEVFN_ROOT);
if (!conf->tcc_offset)
return;