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mb/siemens/mc_apl1: Use pci_or_config16 function

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Change-Id: I93e09fc9801f6d32cade351bac0cba82f671acfe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: siemens-bot
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This commit is contained in:
Angel Pons
2020-11-10 20:07:33 +01:00
parent 16c06c273c
commit 28ed7878f0
5 changed files with 5 additions and 20 deletions
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5
src/mainboard/siemens/mc_apl1/mainboard.c
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@@ -187,7 +187,6 @@ static void mainboard_init(void *chip_info)
static void mainboard_final(void *chip_info) static void mainboard_final(void *chip_info)
{ {
uint16_t cmd = 0;
struct device *dev = NULL; struct device *dev = NULL;
/* Do board specific things */ /* Do board specific things */
@@ -196,9 +195,7 @@ static void mainboard_final(void *chip_info)
/* Set Master Enable for on-board PCI device. */ /* Set Master Enable for on-board PCI device. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0);
if (dev) { if (dev) {
cmd = pci_read_config16(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, cmd);
} }
/* Set up SPI OPCODE menu before the controller is locked. */ /* Set up SPI OPCODE menu before the controller is locked. */
fast_spi_set_opcode_menu(); fast_spi_set_opcode_menu();

5
src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
View File

@@ -16,14 +16,11 @@
void variant_mainboard_final(void) void variant_mainboard_final(void)
{ {
struct device *dev; struct device *dev;
uint16_t cmd = 0;
/* Set Master Enable for on-board PCI device. */ /* Set Master Enable for on-board PCI device. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
if (dev) { if (dev) {
cmd = pci_read_config16(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, cmd);
} }
} }

5
src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
View File

@@ -22,7 +22,6 @@
void variant_mainboard_final(void) void variant_mainboard_final(void)
{ {
struct device *dev = NULL; struct device *dev = NULL;
uint16_t cmd = 0;
/* PIR6 register mapping for PCIe root ports /* PIR6 register mapping for PCIe root ports
* INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC#
@@ -43,9 +42,7 @@ void variant_mainboard_final(void)
/* Set Master Enable for on-board PCI device. */ /* Set Master Enable for on-board PCI device. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
if (dev) { if (dev) {
cmd = pci_read_config16(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, cmd);
/* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream
* XIO2001 PCIe to PCI Bridge. * XIO2001 PCIe to PCI Bridge.

5
src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
View File

@@ -20,7 +20,6 @@
void variant_mainboard_final(void) void variant_mainboard_final(void)
{ {
struct device *dev = NULL; struct device *dev = NULL;
uint16_t cmd;
/* /*
* PIR6 register mapping for PCIe root ports * PIR6 register mapping for PCIe root ports
@@ -50,9 +49,7 @@ void variant_mainboard_final(void)
/* Set Master Enable for on-board PCI device. */ /* Set Master Enable for on-board PCI device. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
if (dev) { if (dev) {
cmd = pci_read_config16(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, cmd);
/* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe /* Disable clock outputs 0-3 (CLKOUT) for upstream XIO2001 PCIe
* to PCI Bridge. */ * to PCI Bridge. */

5
src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
View File

@@ -22,7 +22,6 @@
void variant_mainboard_final(void) void variant_mainboard_final(void)
{ {
struct device *dev = NULL; struct device *dev = NULL;
uint16_t cmd = 0;
/* PIR6 register mapping for PCIe root ports /* PIR6 register mapping for PCIe root ports
* INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC#
@@ -43,9 +42,7 @@ void variant_mainboard_final(void)
/* Set Master Enable for on-board PCI device. */ /* Set Master Enable for on-board PCI device. */
dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0);
if (dev) { if (dev) {
cmd = pci_read_config16(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
cmd |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, cmd);
/* Disable clock outputs 0-3 (CLKOUT) for upstream /* Disable clock outputs 0-3 (CLKOUT) for upstream
* XIO2001 PCIe to PCI Bridge. * XIO2001 PCIe to PCI Bridge.