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F14 mainboard: mptable update

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Add GNB internal graphic interrupt,
correct southbridge hd audio device interrupt. and remove the
dead code already commented out.

south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.

Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/451
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
Kerry Sheh
2011-12-22 12:18:26 +08:00
committed by Marc Jones
parent d6ed09b7ec
commit 28f171096b
5 changed files with 27 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/mainboard/amd/inagua/mptable.c
View File

@@ -166,11 +166,15 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio */
PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
/* Southbridge HD Audio */
PCI_INT(0x0, 0x14, 0x2, intr_data[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
@@ -179,7 +183,7 @@ static void *smp_write_config_table(void *v)
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
PCI_INT(0x0, 0x14, 0x5, intr_data[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);

8
src/mainboard/amd/persimmon/mptable.c
View File

@@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, fn, pin)
#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
@@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v)
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI slots */

8
src/mainboard/amd/south_station/mptable.c
View File

@@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, fn, pin)
#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
@@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v)
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI slots */

8
src/mainboard/amd/union_station/mptable.c
View File

@@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, fn, pin)
#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
@@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v)
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI slots */

8
src/mainboard/asrock/e350m1/mptable.c
View File

@@ -90,9 +90,13 @@ static void *smp_write_config_table(void *v)
#define PCI_INT(bus, dev, fn, pin)
#endif
/* APU Internal Graphic Device*/
PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* HD Audio: */
/* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
@@ -105,8 +109,6 @@ static void *smp_write_config_table(void *v)
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* PCI_INT(0x0, 0x14, 0x2, 0x12); */
/* on board NIC & Slot PCIE. */
/* PCI slots */