soc/intel/denverton_ns: Enable common block PMC

Mainly update headers to build.

Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.

Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

src/soc/intel/common/block/pmc/Kconfig

@@ -37,3 +37,11 @@ config PMC_INVALID_READ_AFTER_WRITE
 	help
 	  Enable this for PMC devices where a read back of ACPI BAR and
 	  IO access bit does not return the previously written value.
+
+config PMC_GLOBAL_RESET_ENABLE_LOCK
+	bool
+	help
+	  Enable this for PMC devices where the reset configuration
+	  and lock register is located under PMC BASE at offset ETR.
+	  Note that the reset register is still at 0xCF9 this only
+	  controls the enable and lock feature.

src/soc/intel/common/block/pmc/pmclib.c

@@ -419,6 +419,7 @@ int pmc_fill_power_state(struct chipset_power_state *ps)
 	return ps->prev_sleep_state;
 }
 
+#if IS_ENABLED(CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK)
 /*
  * If possible, lock 0xcf9. Once the register is locked, it can't be changed.
  * This lock is reset on cold boot, hard reset, soft reset and Sx.
@@ -451,6 +452,7 @@ void pmc_global_reset_enable(bool enable)
 	reg = enable ? reg | CF9_GLB_RST : reg & ~CF9_GLB_RST;
 	write32((void *)etr, reg);
 }
+#endif // CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK
 
 int vboot_platform_is_resuming(void)
 {