soc/intel/denverton_ns: Enable common block PMC

Mainly update headers to build.

Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.

Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>

src/soc/intel/skylake/Kconfig

@@ -51,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
 	select SA_ENABLE_DPR
 	select SMM_TSEG
 	select SMP
+	select PMC_GLOBAL_RESET_ENABLE_LOCK
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK