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soc/intel/alderlake/romstage: Do initial SoC commit till romstage

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List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Add SA EDS document number and chapter number
4. Fill required FSP-M UPD to call FSP-M API

Change-Id: I4473aed27363c22e92e66cc6770cb55aae83e75c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik
2020-09-09 13:34:18 +05:30
parent eb17b475c8
commit 292afef2fb
19 changed files with 1471 additions and 0 deletions
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30
src/soc/intel/alderlake/Kconfig
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@@ -8,15 +8,22 @@ if SOC_INTEL_ALDERLAKE
config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_BOOTBLOCK_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_VERSTAGE_X86_32
select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
select BOOT_DEVICE_SUPPORTS_WRITES
select CACHE_MRC_SETTINGS
select CPU_INTEL_COMMON
select FSP_M_XIP
select INTEL_DESCRIPTOR_MODE_CAPABLE
select IDT_IN_EVERY_STAGE
select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED
select MRC_SETTINGS_PROTECT
select MICROCODE_BLOB_UNDISCLOSED
select PLATFORM_USES_FSP2_2
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_SA
@@ -120,6 +127,13 @@ config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL
config CHROMEOS
select CHROMEOS_RAMOOPS_DYNAMIC
config VBOOT
select VBOOT_SEPARATE_VERSTAGE
select VBOOT_MUST_REQUEST_DISPLAY
select VBOOT_STARTS_IN_BOOTBLOCK
select VBOOT_VBNV_CMOS
select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH
config C_ENV_BOOTBLOCK_SIZE
hex
default 0xC000
@@ -139,4 +153,20 @@ config FSP_FD_PATH
string
depends on FSP_USE_REPO
default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd"
config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT
int "Debug Consent for ADL"
# USB DBC is more common for developers so make this default to 3 if
# SOC_INTEL_DEBUG_CONSENT=y
default 3 if SOC_INTEL_DEBUG_CONSENT
default 0
help
This is to control debug interface on SOC.
Setting non-zero value will allow to use DBC or DCI to debug SOC.
PlatformDebugConsent in FspmUpd.h has the details.
Desired platform debug type are
0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB),
3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC),
6:Enable (2-wire DCI OOB), 7:Manual
endif