mb/system76/rpl: Add Adder WS 4 as a variant
The Adder WS 4 (addw4) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with Crucial CT8G48C40S5) - M.2 NVMe SSDs - All USB ports - MicroSD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Linux 6.8 - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.8.0 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Detection of devices in TBT slot on boot Change-Id: I4a6819cbcf64f68237008adebdd7eb196336514c Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82595 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tim Crawford
committed by
Felix Singer
Felix Singer
parent
8b9716e226
commit
29f1b79127
@@ -32,6 +32,12 @@ config BOARD_SYSTEM76_ADDW3
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select PCIEXP_HOTPLUG
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select PCIEXP_HOTPLUG
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select SOC_INTEL_ALDERLAKE_PCH_S
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select SOC_INTEL_ALDERLAKE_PCH_S
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config BOARD_SYSTEM76_ADDW4
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select BOARD_SYSTEM76_RPL_COMMON
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select EC_SYSTEM76_EC_DGPU
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select PCIEXP_HOTPLUG
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select SOC_INTEL_ALDERLAKE_PCH_S
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config BOARD_SYSTEM76_BONW15
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config BOARD_SYSTEM76_BONW15
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select BOARD_SYSTEM76_RPL_COMMON
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select BOARD_SYSTEM76_RPL_COMMON
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select EC_SYSTEM76_EC_DGPU
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select EC_SYSTEM76_EC_DGPU
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@@ -85,6 +91,7 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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config VARIANT_DIR
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "addw4" if BOARD_SYSTEM76_ADDW4
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "darp9" if BOARD_SYSTEM76_DARP9
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default "darp9" if BOARD_SYSTEM76_DARP9
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default "galp7" if BOARD_SYSTEM76_GALP7
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default "galp7" if BOARD_SYSTEM76_GALP7
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@@ -99,6 +106,7 @@ config OVERRIDE_DEVICETREE
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config MAINBOARD_PART_NUMBER
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config MAINBOARD_PART_NUMBER
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "addw4" if BOARD_SYSTEM76_ADDW4
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "darp9" if BOARD_SYSTEM76_DARP9
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default "darp9" if BOARD_SYSTEM76_DARP9
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default "galp7" if BOARD_SYSTEM76_GALP7
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default "galp7" if BOARD_SYSTEM76_GALP7
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@@ -109,7 +117,7 @@ config MAINBOARD_PART_NUMBER
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default "serw13" if BOARD_SYSTEM76_SERW13
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default "serw13" if BOARD_SYSTEM76_SERW13
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Adder WS" if BOARD_SYSTEM76_ADDW3
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default "Adder WS" if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4
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default "Bonobo WS" if BOARD_SYSTEM76_BONW15
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default "Bonobo WS" if BOARD_SYSTEM76_BONW15
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default "Darter Pro" if BOARD_SYSTEM76_DARP9
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default "Darter Pro" if BOARD_SYSTEM76_DARP9
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default "Galago Pro" if BOARD_SYSTEM76_GALP7
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default "Galago Pro" if BOARD_SYSTEM76_GALP7
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@@ -120,6 +128,7 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
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config MAINBOARD_VERSION
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config MAINBOARD_VERSION
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "addw4" if BOARD_SYSTEM76_ADDW4
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "darp9" if BOARD_SYSTEM76_DARP9
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default "darp9" if BOARD_SYSTEM76_DARP9
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default "galp7" if BOARD_SYSTEM76_GALP7
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default "galp7" if BOARD_SYSTEM76_GALP7
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@@ -3,6 +3,9 @@
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config BOARD_SYSTEM76_ADDW3
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config BOARD_SYSTEM76_ADDW3
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bool "addw3"
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bool "addw3"
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config BOARD_SYSTEM76_ADDW4
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bool "addw3"
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config BOARD_SYSTEM76_BONW15
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config BOARD_SYSTEM76_BONW15
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bool "bonw15"
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bool "bonw15"
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@@ -53,7 +53,7 @@ chip soc/intel/alderlake
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register "sata_salp_support" = "1"
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register "sata_salp_support" = "1"
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register "sata_ports_enable[1]" = "1" # SSD1
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register "sata_ports_enable[1]" = "1" # SSD1
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# FIXME: DevSlp breaks S0ix
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# FIXME: DevSlp breaks S0ix
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#register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1)
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#register "sata_ports_dev_slp[1]" = "1"
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end
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end
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device ref pch_espi on
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device ref pch_espi on
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register "gen1_dec" = "0x00040069" # EC PM channel
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register "gen1_dec" = "0x00040069" # EC PM channel
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12
src/mainboard/system76/rpl/variants/addw4/board.fmd
Normal file
12
src/mainboard/system76/rpl/variants/addw4/board.fmd
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@@ -0,0 +1,12 @@
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FLASH 32M {
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SI_DESC 4K
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SI_ME 3944K
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SI_BIOS@16M 16M {
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RW_MRC_CACHE 64K
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SMMSTORE(PRESERVE) 256K
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WP_RO {
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FMAP 4K
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COREBOOT(CBFS)
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}
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}
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}
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2
src/mainboard/system76/rpl/variants/addw4/board_info.txt
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2
src/mainboard/system76/rpl/variants/addw4/board_info.txt
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@@ -0,0 +1,2 @@
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Board name: addw4
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Release year: 2024
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BIN
src/mainboard/system76/rpl/variants/addw4/data.vbt
Normal file
BIN
src/mainboard/system76/rpl/variants/addw4/data.vbt
Normal file
Binary file not shown.
294
src/mainboard/system76/rpl/variants/addw4/gpio.c
Normal file
294
src/mainboard/system76/rpl/variants/addw4/gpio.c
Normal file
@@ -0,0 +1,294 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW#
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
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PAD_NC(GPD2, NONE),
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
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PAD_NC(GPD6, NONE),
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PAD_NC(GPD7, NONE),
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK
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PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
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PAD_NC(GPD10, NONE),
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PAD_NC(GPD11, NONE),
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PAD_NC(GPD12, NONE),
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
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PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
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PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
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PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
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PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
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PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET#
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PAD_NC(GPP_A7, NONE),
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PAD_NC(GPP_A8, NONE),
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PAD_NC(GPP_A9, NONE),
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PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // ESPI_ALRT0#
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PAD_CFG_GPI(GPP_A11, UP_20K, DEEP), // GPIO4_GC6_NVVDD_EN_R
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PAD_NC(GPP_A12, NONE),
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PAD_NC(GPP_A13, NONE),
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PAD_NC(GPP_A14, NONE),
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/* ------- GPIO Group GPP_B ------- */
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_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // TPM_PIRQ#
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PAD_NC(GPP_B1, NONE),
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PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE#
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PAD_CFG_GPO(GPP_B3, 1, PLTRST), // BT_EN
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PAD_NC(GPP_B4, NONE),
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PAD_NC(GPP_B5, NONE),
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PAD_NC(GPP_B6, NONE),
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PAD_NC(GPP_B7, NONE),
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PAD_NC(GPP_B8, NONE),
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PAD_NC(GPP_B9, NONE),
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PAD_NC(GPP_B10, NONE),
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PAD_NC(GPP_B11, NONE),
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PAD_NC(GPP_B12, NONE),
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR
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PAD_NC(GPP_B15, NONE),
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT#
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PAD_NC(GPP_B19, NONE),
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PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3
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PAD_NC(GPP_B21, NONE),
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PAD_NC(GPP_B22, NONE),
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PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal freq strap
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
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PAD_CFG_GPI(GPP_C2, NONE, DEEP), // TLS confidentiality strap
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // I2C2_SDA (Pantone)
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // I2C2_SCL (Pantone)
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PAD_NC(GPP_C5, NONE), // eSPI disable strap
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), // SMD_7411
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), // SMC_7411
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PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
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PAD_NC(GPP_C9, NONE),
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PAD_CFG_GPO(GPP_C10, 0, DEEP), // TEST_R (ANX7411)
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PAD_CFG_GPO(GPP_C11, 0, DEEP), // PCH_TEST_R_2 (ANX7411)
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PAD_NC(GPP_C12, NONE),
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PAD_NC(GPP_C13, NONE),
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PAD_NC(GPP_C14, NONE),
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PAD_NC(GPP_C15, NONE),
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // SMD_7411_2
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // SMC_7411_2
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// GPP_C20 (UART2_RXD) configured in bootblock
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// GPP_C21 (UART2_TXD) configured in bootblock
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PAD_NC(GPP_C22, NONE),
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PAD_NC(GPP_C23, NONE),
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/* ------- GPIO Group GPP_D ------- */
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PAD_NC(GPP_D0, NONE),
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PAD_NC(GPP_D1, NONE),
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PAD_NC(GPP_D2, NONE),
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PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP
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PAD_NC(GPP_D4, NONE),
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PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N
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// GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP
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PAD_NC(GPP_D7, NONE),
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PAD_NC(GPP_D8, NONE),
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PAD_NC(GPP_D9, NONE),
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PAD_NC(GPP_D10, NONE),
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PAD_NC(GPP_D11, NONE),
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// GPP_D12 (SSD2_CLKREQ#) configured by FSP
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PAD_NC(GPP_D13, NONE),
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PAD_NC(GPP_D14, NONE),
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_NC(GPP_D18, NONE),
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PAD_NC(GPP_D19, NONE),
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PAD_NC(GPP_D20, NONE),
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PAD_NC(GPP_D21, NONE),
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PAD_NC(GPP_D22, NONE),
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Group GPP_E ------- */
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PAD_NC(GPP_E0, NONE),
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PAD_NC(GPP_E1, NONE),
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PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI#
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PAD_NC(GPP_E3, NONE),
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PAD_NC(GPP_E4, NONE),
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PAD_NC(GPP_E5, NONE),
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PAD_NC(GPP_E6, NONE),
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PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN#
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
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PAD_CFG_GPI(GPP_E9, NONE, DEEP), // USB_OC0#
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PAD_CFG_GPI(GPP_E10, NONE, DEEP), // USB_OC1#
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PAD_CFG_GPI(GPP_E11, NONE, DEEP), // USB_OC2#
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PAD_CFG_GPI(GPP_E12, NONE, DEEP), // USB_OC3#
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PAD_NC(GPP_E13, NONE),
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PAD_NC(GPP_E14, NONE),
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PAD_NC(GPP_E15, NONE),
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PAD_NC(GPP_E16, NONE),
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PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST#
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PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON
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PAD_NC(GPP_E19, NONE),
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PAD_NC(GPP_E20, NONE),
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PAD_NC(GPP_E21, NONE),
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/* ------- GPIO Group GPP_F ------- */
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // M.2_SSD_SATA_DET_N
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PAD_NC(GPP_F1, NONE),
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PAD_NC(GPP_F2, NONE),
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PAD_NC(GPP_F3, NONE),
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PAD_NC(GPP_F4, NONE),
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PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // SSD_SATA_DEVSLP
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PAD_NC(GPP_F6, NONE),
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_PAD_CFG_STRUCT(GPP_F7, 0x80100100, 0x0000), // 7411_INTP_OUT
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PAD_NC(GPP_F8, NONE),
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// GPP_F9 (DGPU_PWR_EN) configured in bootblock
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PAD_CFG_GPI(GPP_F10, NONE, DEEP), // Recovery strap
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PAD_NC(GPP_F11, NONE),
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PAD_NC(GPP_F12, NONE),
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PAD_NC(GPP_F13, NONE),
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PAD_NC(GPP_F14, NONE),
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PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N
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_PAD_CFG_STRUCT(GPP_F16, 0x80100100, 0x0000), // INTP_OUT
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PAD_NC(GPP_F17, NONE),
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PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_WP#
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
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PAD_NC(GPP_F22, NONE),
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PAD_NC(GPP_F23, NONE),
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/* ------- GPIO Group GPP_G ------- */
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||||||
|
PAD_CFG_GPO(GPP_G0, 0, DEEP), // Board ID 2
|
||||||
|
PAD_CFG_GPO(GPP_G1, 0, DEEP), // Board ID 3
|
||||||
|
PAD_NC(GPP_G2, NONE),
|
||||||
|
PAD_CFG_GPI(GPP_G3, NONE, DEEP), // MB detect GN20/GN21
|
||||||
|
PAD_CFG_GPI(GPP_G4, NONE, DEEP), // Board ID 1
|
||||||
|
PAD_NC(GPP_G5, NONE),
|
||||||
|
PAD_CFG_GPI(GPP_G6, NONE, DEEP), // MB detect G-SYNC
|
||||||
|
PAD_CFG_GPI(GPP_G7, NONE, DEEP), // MB detect 230W/180W adapter
|
||||||
|
|
||||||
|
/* ------- GPIO Group GPP_H ------- */
|
||||||
|
PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP
|
||||||
|
PAD_CFG_GPO(GPP_H1, 0, DEEP), // Pantone detect
|
||||||
|
PAD_CFG_GPI(GPP_H2, NONE, DEEP), // WLAN_GPIO_WAKE_N
|
||||||
|
// GPP_H3 (NC) configured by FSP
|
||||||
|
// GPP_H4 (SSD1_SATA_CLKREQ#) configured by FSP
|
||||||
|
// GPP_H5 (WLAN_CLKREQ#) configured by FSP
|
||||||
|
// GPP_H6 (NC) configured by FSP
|
||||||
|
// GPP_H7 (LAN_CLKREQ#) configured by FSP
|
||||||
|
// GPP_H8 (PEG_CLKREQ#) configured by FSP
|
||||||
|
// GPP_H9 (SSD3_CLKREQ#) configured by FSP
|
||||||
|
PAD_NC(GPP_H10, NONE),
|
||||||
|
PAD_NC(GPP_H11, NONE),
|
||||||
|
PAD_NC(GPP_H12, NONE),
|
||||||
|
PAD_NC(GPP_H13, NONE),
|
||||||
|
PAD_NC(GPP_H14, NONE),
|
||||||
|
PAD_CFG_GPO(GPP_H15, 0, DEEP), // JTAG ODT strap
|
||||||
|
PAD_NC(GPP_H16, NONE),
|
||||||
|
PAD_NC(GPP_H17, NONE),
|
||||||
|
PAD_CFG_GPO(GPP_H18, 0, DEEP), // 1.8V VCCPSPI strap
|
||||||
|
PAD_NC(GPP_H19, NONE),
|
||||||
|
PAD_NC(GPP_H20, NONE),
|
||||||
|
PAD_NC(GPP_H21, NONE),
|
||||||
|
PAD_NC(GPP_H22, NONE),
|
||||||
|
PAD_NC(GPP_H23, NONE),
|
||||||
|
|
||||||
|
/* ------- GPIO Group GPP_I ------- */
|
||||||
|
PAD_NC(GPP_I0, NONE),
|
||||||
|
PAD_CFG_NF(GPP_I1, NONE, DEEP, NF1), // DP_HPD
|
||||||
|
PAD_CFG_NF(GPP_I2, NONE, DEEP, NF1), // HDMI_HPD
|
||||||
|
PAD_NC(GPP_I3, NONE),
|
||||||
|
PAD_NC(GPP_I4, NONE),
|
||||||
|
PAD_NC(GPP_I5, NONE),
|
||||||
|
PAD_NC(GPP_I6, NONE),
|
||||||
|
PAD_NC(GPP_I7, NONE),
|
||||||
|
PAD_NC(GPP_I8, NONE),
|
||||||
|
PAD_NC(GPP_I9, NONE),
|
||||||
|
PAD_NC(GPP_I10, NONE),
|
||||||
|
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // USB_OC4#
|
||||||
|
PAD_CFG_GPI(GPP_I12, NONE, DEEP), // USB_OC5#
|
||||||
|
PAD_CFG_GPI(GPP_I13, NONE, DEEP), // USB_OC6#
|
||||||
|
PAD_CFG_GPI(GPP_I14, NONE, DEEP), // USB_OC7#
|
||||||
|
PAD_NC(GPP_I15, NONE),
|
||||||
|
PAD_NC(GPP_I16, NONE),
|
||||||
|
PAD_NC(GPP_I17, NONE),
|
||||||
|
PAD_CFG_GPO(GPP_I18, 0, DEEP), // No reboot strap
|
||||||
|
PAD_NC(GPP_I19, NONE),
|
||||||
|
PAD_NC(GPP_I20, NONE),
|
||||||
|
PAD_NC(GPP_I21, NONE),
|
||||||
|
PAD_CFG_GPO(GPP_I22, 0, DEEP), // Boot BIOS strap
|
||||||
|
|
||||||
|
/* ------- GPIO Group GPP_J ------- */
|
||||||
|
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
|
||||||
|
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE#
|
||||||
|
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT_R / Xtal freq strap
|
||||||
|
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||||
|
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT_R / M.2 CNV modes strap
|
||||||
|
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||||
|
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||||
|
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||||
|
PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU
|
||||||
|
PAD_NC(GPP_J9, NONE),
|
||||||
|
PAD_NC(GPP_J10, NONE),
|
||||||
|
PAD_NC(GPP_J11, NONE),
|
||||||
|
|
||||||
|
/* ------- GPIO Group GPP_K ------- */
|
||||||
|
PAD_NC(GPP_K0, NONE),
|
||||||
|
PAD_NC(GPP_K1, NONE),
|
||||||
|
PAD_NC(GPP_K2, NONE),
|
||||||
|
PAD_NC(GPP_K3, NONE),
|
||||||
|
PAD_NC(GPP_K4, NONE),
|
||||||
|
PAD_NC(GPP_K5, NONE),
|
||||||
|
// GPP_K6 not in schematics
|
||||||
|
// GPP_K7 not in schematics
|
||||||
|
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0
|
||||||
|
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1
|
||||||
|
// GPP_K10 not in schematics
|
||||||
|
PAD_NC(GPP_K11, NONE),
|
||||||
|
|
||||||
|
/* ------- GPIO Group GPP_R ------- */
|
||||||
|
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
|
||||||
|
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||||
|
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
|
||||||
|
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
|
||||||
|
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#_R
|
||||||
|
PAD_NC(GPP_R5, NONE),
|
||||||
|
PAD_NC(GPP_R6, NONE),
|
||||||
|
PAD_NC(GPP_R7, NONE),
|
||||||
|
PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD
|
||||||
|
PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD
|
||||||
|
PAD_NC(GPP_R10, NONE),
|
||||||
|
PAD_NC(GPP_R11, NONE),
|
||||||
|
PAD_NC(GPP_R12, NONE),
|
||||||
|
PAD_NC(GPP_R13, NONE),
|
||||||
|
PAD_NC(GPP_R14, NONE),
|
||||||
|
PAD_NC(GPP_R15, NONE),
|
||||||
|
// GPP_R16 (DGPU_RST#_PCH) configured in bootblock
|
||||||
|
PAD_NC(GPP_R17, NONE),
|
||||||
|
PAD_NC(GPP_R18, NONE),
|
||||||
|
PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI#
|
||||||
|
PAD_NC(GPP_R20, NONE),
|
||||||
|
PAD_NC(GPP_R21, NONE),
|
||||||
|
|
||||||
|
/* ------- GPIO Group GPP_S ------- */
|
||||||
|
PAD_NC(GPP_S0, NONE),
|
||||||
|
PAD_NC(GPP_S1, NONE),
|
||||||
|
PAD_NC(GPP_S2, NONE),
|
||||||
|
PAD_NC(GPP_S3, NONE),
|
||||||
|
PAD_NC(GPP_S4, NONE),
|
||||||
|
PAD_NC(GPP_S5, NONE),
|
||||||
|
PAD_NC(GPP_S6, NONE),
|
||||||
|
PAD_NC(GPP_S7, NONE),
|
||||||
|
};
|
||||||
|
|
||||||
|
void mainboard_configure_gpios(void)
|
||||||
|
{
|
||||||
|
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||||
|
}
|
||||||
16
src/mainboard/system76/rpl/variants/addw4/gpio_early.c
Normal file
16
src/mainboard/system76/rpl/variants/addw4/gpio_early.c
Normal file
@@ -0,0 +1,16 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
|
||||||
|
#include <mainboard/gpio.h>
|
||||||
|
#include <soc/gpio.h>
|
||||||
|
|
||||||
|
static const struct pad_config early_gpio_table[] = {
|
||||||
|
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||||
|
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||||
|
PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
|
||||||
|
PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH
|
||||||
|
};
|
||||||
|
|
||||||
|
void mainboard_configure_early_gpios(void)
|
||||||
|
{
|
||||||
|
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||||
|
}
|
||||||
52
src/mainboard/system76/rpl/variants/addw4/hda_verb.c
Normal file
52
src/mainboard/system76/rpl/variants/addw4/hda_verb.c
Normal file
@@ -0,0 +1,52 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
|
||||||
|
#include <device/azalia_device.h>
|
||||||
|
|
||||||
|
const u32 cim_verb_data[] = {
|
||||||
|
/* Realtek, ALC245 */
|
||||||
|
0x10ec0245, /* Vendor ID */
|
||||||
|
0x15580353, /* Subsystem ID */
|
||||||
|
35, /* Number of entries */
|
||||||
|
|
||||||
|
0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb,
|
||||||
|
|
||||||
|
AZALIA_SUBVENDOR(0, 0x15580353),
|
||||||
|
AZALIA_RESET(1),
|
||||||
|
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||||
|
AZALIA_PIN_CFG(0, 0x13, 0x40000000),
|
||||||
|
AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||||
|
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0, 0x1b, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0, 0x1d, 0x40689b2d),
|
||||||
|
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||||
|
AZALIA_PIN_CFG(0, 0x21, 0x04211020),
|
||||||
|
|
||||||
|
0x05b50006, 0x05b40011, 0x0205001a, 0x0204810b,
|
||||||
|
0x0205004a, 0x02042010, 0x02050038, 0x02047909,
|
||||||
|
0x05c50000, 0x05c43d82, 0x05c50000, 0x05c43d82,
|
||||||
|
0x05350000, 0x0534201a, 0x05350000, 0x0534201a,
|
||||||
|
0x0535001d, 0x05340800, 0x0535001e, 0x05340800,
|
||||||
|
0x05350003, 0x05341ec4, 0x05350004, 0x05340000,
|
||||||
|
0x05450000, 0x05442000, 0x0545001d, 0x05440800,
|
||||||
|
0x0545001e, 0x05440800, 0x05450003, 0x05441ec4,
|
||||||
|
0x05450004, 0x05440000, 0x05350000, 0x0534a01a,
|
||||||
|
0x0205003c, 0x0204f175, 0x0205003c, 0x0204f135,
|
||||||
|
0x02050040, 0x02048800, 0x05a50001, 0x05a4001f,
|
||||||
|
0x02050010, 0x02040020, 0x02050010, 0x02040020,
|
||||||
|
0x0205006b, 0x0204a390, 0x0205006b, 0x0204a390,
|
||||||
|
0x0205006c, 0x02040c9e, 0x0205006d, 0x02040c00,
|
||||||
|
0x00170500, 0x00170500, 0x05a50004, 0x05a40113,
|
||||||
|
0x02050008, 0x02046a8c, 0x02050076, 0x0204f000,
|
||||||
|
0x0205000e, 0x020465c0, 0x02050033, 0x02048580,
|
||||||
|
0x02050069, 0x0204fda8, 0x02050068, 0x02040000,
|
||||||
|
0x02050003, 0x02040002, 0x02050069, 0x02040000,
|
||||||
|
0x02050068, 0x02040001, 0x0205002e, 0x0204290e,
|
||||||
|
0x02050010, 0x02040020, 0x02050010, 0x02040020,
|
||||||
|
};
|
||||||
|
|
||||||
|
const u32 pc_beep_verbs[] = {};
|
||||||
|
|
||||||
|
AZALIA_ARRAY_SIZES;
|
||||||
103
src/mainboard/system76/rpl/variants/addw4/overridetree.cb
Normal file
103
src/mainboard/system76/rpl/variants/addw4/overridetree.cb
Normal file
@@ -0,0 +1,103 @@
|
|||||||
|
# SPDX-License-Identifier: GPL-2.0-only
|
||||||
|
|
||||||
|
chip soc/intel/alderlake
|
||||||
|
# Support 5600 MT/s memory
|
||||||
|
register "max_dram_speed_mts" = "5600"
|
||||||
|
|
||||||
|
device domain 0 on
|
||||||
|
subsystemid 0x1558 0x0353 inherit
|
||||||
|
|
||||||
|
device ref xhci on
|
||||||
|
register "usb2_ports" = "{
|
||||||
|
/* Port reset messaging cannot be used,
|
||||||
|
* so do not use USB2_PORT_TYPE_C for these */
|
||||||
|
[0] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC1 */
|
||||||
|
[1] = USB2_PORT_MID(OC_SKIP), /* J_TYPEC2 */
|
||||||
|
[2] = USB2_PORT_MID(OC_SKIP), /* J_USB2 */
|
||||||
|
[3] = USB2_PORT_MID(OC_SKIP), /* J_USB1 (Audio board) */
|
||||||
|
[6] = USB2_PORT_MID(OC_SKIP), /* Fingerprint */
|
||||||
|
[7] = USB2_PORT_MID(OC_SKIP), /* Camera */
|
||||||
|
[13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
|
||||||
|
}"
|
||||||
|
|
||||||
|
register "usb3_ports" = "{
|
||||||
|
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */
|
||||||
|
[1] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-C */
|
||||||
|
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB2 */
|
||||||
|
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* J_USB1 (Audio board) */
|
||||||
|
}"
|
||||||
|
end
|
||||||
|
|
||||||
|
device ref i2c0 on
|
||||||
|
# Touchpad I2C bus
|
||||||
|
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""ELAN0412""
|
||||||
|
register "generic.desc" = ""ELAN Touchpad""
|
||||||
|
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
|
||||||
|
register "generic.detect" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x01"
|
||||||
|
device i2c 15 on end
|
||||||
|
end
|
||||||
|
chip drivers/i2c/hid
|
||||||
|
register "generic.hid" = ""FTCS1000""
|
||||||
|
register "generic.desc" = ""FocalTech Touchpad""
|
||||||
|
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
|
||||||
|
register "generic.detect" = "1"
|
||||||
|
register "hid_desc_reg_offset" = "0x01"
|
||||||
|
device i2c 38 on end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
device ref pcie5_0 on
|
||||||
|
# DGPU
|
||||||
|
register "cpu_pcie_rp[CPU_RP(2)]" = "{
|
||||||
|
.clk_src = 14,
|
||||||
|
.clk_req = 14,
|
||||||
|
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||||
|
}"
|
||||||
|
end
|
||||||
|
|
||||||
|
device ref pcie_rp3 on
|
||||||
|
# GLAN
|
||||||
|
register "pch_pcie_rp[PCH_RP(3)]" = "{
|
||||||
|
.clk_src = 13,
|
||||||
|
.clk_req = 13,
|
||||||
|
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||||
|
}"
|
||||||
|
device pci 00.0 on end # Realtek RTL8111H
|
||||||
|
end
|
||||||
|
device ref pcie_rp8 on
|
||||||
|
# WLAN
|
||||||
|
register "pch_pcie_rp[PCH_RP(8)]" = "{
|
||||||
|
.clk_src = 11,
|
||||||
|
.clk_req = 11,
|
||||||
|
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||||
|
}"
|
||||||
|
end
|
||||||
|
device ref pcie_rp13 on
|
||||||
|
# J_SSD1
|
||||||
|
register "pch_pcie_rp[PCH_RP(13)]" = "{
|
||||||
|
.clk_src = 10,
|
||||||
|
.clk_req = 10,
|
||||||
|
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||||
|
}"
|
||||||
|
end
|
||||||
|
device ref pcie_rp21 on
|
||||||
|
# J_SSD2
|
||||||
|
register "pch_pcie_rp[PCH_RP(21)]" = "{
|
||||||
|
.clk_src = 5,
|
||||||
|
.clk_req = 5,
|
||||||
|
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||||
|
}"
|
||||||
|
end
|
||||||
|
device ref pcie_rp25 on
|
||||||
|
# J_SSD3
|
||||||
|
register "pch_pcie_rp[PCH_RP(25)]" = "{
|
||||||
|
.clk_src = 15,
|
||||||
|
.clk_req = 15,
|
||||||
|
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||||
|
}"
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
32
src/mainboard/system76/rpl/variants/addw4/romstage.c
Normal file
32
src/mainboard/system76/rpl/variants/addw4/romstage.c
Normal file
@@ -0,0 +1,32 @@
|
|||||||
|
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||||
|
|
||||||
|
#include <soc/meminit.h>
|
||||||
|
#include <soc/romstage.h>
|
||||||
|
|
||||||
|
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||||
|
{
|
||||||
|
const struct mb_cfg board_cfg = {
|
||||||
|
.type = MEM_TYPE_DDR5,
|
||||||
|
.ect = true,
|
||||||
|
.LpDdrDqDqsReTraining = 1,
|
||||||
|
.ddr_config = {
|
||||||
|
.dq_pins_interleaved = true,
|
||||||
|
},
|
||||||
|
};
|
||||||
|
const struct mem_spd spd_info = {
|
||||||
|
.topo = MEM_TOPO_DIMM_MODULE,
|
||||||
|
.smbus = {
|
||||||
|
[0] = { .addr_dimm[0] = 0x50, },
|
||||||
|
[1] = { .addr_dimm[0] = 0x52, },
|
||||||
|
},
|
||||||
|
};
|
||||||
|
const bool half_populated = false;
|
||||||
|
|
||||||
|
// Set primary display to hybrid graphics
|
||||||
|
mupd->FspmConfig.PrimaryDisplay = 4;
|
||||||
|
|
||||||
|
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
|
||||||
|
mupd->FspmConfig.GpioOverride = 0;
|
||||||
|
|
||||||
|
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
|
||||||
|
}
|
||||||
Reference in New Issue
Block a user