mb/bostentech: Add GBYT4 port

- Single channel DDR3L: requires mrc.bin (extracted from ChromeBook
	firmware)
	- Tested, working with: 2GB SK Hynix stick, 4GB Samsung stick
- VGA: Video works with VGA rom extracted from UEFI
	- SeaBIOS (runs the option rom) tested, works in text mode
	- GRUB2 (coreboot runs the option rom) tested, works in VESA mode,
		no video in text mode
- USB: Both USB2.0 ports work using the EHCI controller
	- Works in both SeaBIOS, GRUB2 and Linux
- Serial: driven by an IT8728F SuperIO
	- Works as a console in coreboot, SeaBIOS and GRUB2
	- Works with interrupts in Linux after a cold boot, after a warm
		reboot IRQs get lost
- SATA: 2 ports on board (one is mSATA)
	- SATA init works with both refcode.elf and native refcode
		(patch CB:43133)
	- Booting from SATA works with GRUB2, SATA works in Linux
	- Patch CB:44088 fixes SATA in SeaBIOS
- 4 PCIe Intel ethernet controllers
	- Only tested in Linux, all 4 work with the igb driver
- Power button, reset button and both indicator LEDs work
- Optional fan header is not tested as the appliance is passively
	cooled
- TXE (ME): optional, does not shut down after 30 minutes without the
	TXE blob
	- Works with TXE blob left as is, shows up on PCI
	- Works with the entire TXE section wiped, no device on PCI,
		intelmetool can't find anything

Used rambi as an example, but almost everything is modified as the two
	boards are very different.

Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Change-Id: I99ed0c94c3255578151f940ad9b274e6f0816bfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/mainboard/bostentech/Kconfig

@@ -0,0 +1,19 @@
+if VENDOR_BOSTENTECH
+
+choice
+	prompt "Mainboard model"
+
+source "src/mainboard/bostentech/*/Kconfig.name"
+
+endchoice
+
+source "src/mainboard/bostentech/*/Kconfig"
+
+config MAINBOARD_VENDOR
+	default "Shenzhen Bostrontium Teng Technology"
+
+config MAINBOARD_FAMILY
+	string
+	default MAINBOARD_PART_NUMBER
+
+endif # VENDOR_BOSTENTECH

src/mainboard/bostentech/Kconfig.name

@@ -0,0 +1,2 @@
+config VENDOR_BOSTENTECH
+	bool "Shenzhen Bostrontium Teng Technology"

src/mainboard/bostentech/gbyt4/Kconfig

@@ -0,0 +1,24 @@
+if BOARD_BOSTENTECH_GBYT4
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select SOC_INTEL_BAYTRAIL
+	select BOARD_ROMSIZE_KB_8192
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select SUPERIO_ITE_IT8728F
+
+config MAINBOARD_DIR
+	string
+	default "bostentech/gbyt4"
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "GBYT4-4L"
+
+config MAINBOARD_SMBIOS_MANUFACTURER
+	string
+	default "Shenzhen Bostrontium Teng Technology"
+
+endif # BOARD_BOSTENTECH_GBYT4

src/mainboard/bostentech/gbyt4/Kconfig.name

@@ -0,0 +1,2 @@
+config BOARD_BOSTENTECH_GBYT4
+	bool "GBYT4"

src/mainboard/bostentech/gbyt4/Makefile.inc

@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += irqroute.c gpio.c
+bootblock-y += early_init.c
+romstage-y += early_init.c

src/mainboard/bostentech/gbyt4/acpi/mainboard.asl

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/*
+ * NOTE: this has to be here even when the board has no LPE audio, otherwise
+ * it breaks the SOC specific ACPI code
+ */
+Scope (\_SB.PCI0.LPEA)
+{
+	Name (GBUF, ResourceTemplate () {})
+}

src/mainboard/bostentech/gbyt4/acpi_tables.c

@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <types.h>
+#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
+
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+	acpi_init_gnvs(gnvs);
+
+	/* Enable USB ports in S3 */
+	gnvs->s3u0 = 1;
+	gnvs->s3u1 = 1;
+
+	/* Disable USB ports in S5 */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* TPM not present */
+	gnvs->tpmp = 0;
+
+	/* Disable DPTF */
+	gnvs->dpte = 0;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	current = acpi_madt_irq_overrides(current);
+
+	return current;
+}
+
+void mainboard_fill_fadt(acpi_fadt_t *fadt)
+{
+	fadt->preferred_pm_profile = PM_DESKTOP;
+}

src/mainboard/bostentech/gbyt4/board_info.txt

@@ -0,0 +1,7 @@
+Vendor name: Shenzhen Bostrontium Teng Technology
+Board name: GBYT4
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y

src/mainboard/bostentech/gbyt4/cmos.layout

@@ -0,0 +1,48 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+388          4       h       0        reboot_counter
+# -----------------------------------------------------------------
+# coreboot config options: console
+395          4       e       6        debug_level
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+# coreboot config options: check sums
+984         16       h       0        check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+6     0     Emergency
+6     1     Alert
+6     2     Critical
+6     3     Error
+6     4     Warning
+6     5     Notice
+6     6     Info
+6     7     Debug
+6     8     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984

src/mainboard/bostentech/gbyt4/devicetree.cb

@@ -0,0 +1,90 @@
+chip soc/intel/baytrail
+
+	register "usb2_comp_bg" = "0x4700"
+
+	# Allow PCIe devices to wake system from suspend
+	register "pcie_wake_enable" = "1"
+
+	# SATA port enable mask (2 ports)
+	register "sata_port_map" = "0x3"
+	register "sata_ahci" = "0x1"
+
+	# Do not route USB ports to XHCI
+	register "usb_route_to_xhci" = "0"
+
+	# USB Port Disable Mask
+	register "usb2_port_disable_mask" = "0x0"
+	register "usb3_port_disable_mask" = "0x0"
+
+	# USB PHY settings
+	register "usb2_per_port_lane0" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+	register "usb2_per_port_lane1" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+	register "usb2_per_port_lane2" = "0x00049209"
+	register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+	register "usb2_per_port_lane3" = "0x00049a09"
+	register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+	# Disable SLP_X stretching after SUS power well fail.
+	register "disable_slp_x_stretch_sus_fail" = "1"
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+	device domain 0 on
+		device pci 00.0 on  end # SoC router
+		device pci 02.0 on  end # GFX
+		device pci 10.0 off end # MMC
+		device pci 11.0 off end # SDIO
+		device pci 12.0 off end # SD
+		device pci 13.0 on  end # SATA
+		device pci 14.0 on  end # XHCI
+		device pci 15.0 off end # LPE
+		device pci 17.0 off end # MMC45
+		device pci 18.0 off end # SIO_DMA1
+		device pci 18.1 off end # I2C1
+		device pci 18.2 off end # I2C2
+		device pci 18.3 off end # I2C3
+		device pci 18.4 off end # I2C4
+		device pci 18.5 off end # I2C5
+		device pci 18.6 off end # I2C6
+		device pci 18.7 off end # I2C7
+		device pci 1a.0 on  end # TXE
+		device pci 1b.0 off end # HDA
+		device pci 1c.0 on  end # PCI-e #1 (LAN1)
+		device pci 1c.1 on  end # PCI-e #2 (LAN2)
+		device pci 1c.2 on  end # PCI-e #3 (LAN3)
+		device pci 1c.3 on  end # PCI-e #4 (LAN4)
+		device pci 1d.0 on  end # EHCI
+		device pci 1e.0 off end # SIO_DMA2
+		device pci 1e.1 off end # PWM1
+		device pci 1e.2 off end # PWM2
+		device pci 1e.3 off end # HSUART1
+		device pci 1e.4 off end # HSUART2
+		device pci 1e.5 off end # SPI
+
+		device pci 1f.0 on      # LPC
+			chip superio/ite/it8728f
+				device pnp 2e.0 off end	# Floppy
+				device pnp 2e.1 on	# COM1
+					io  0x60 = 0x03f8
+					irq 0x70 = 4
+				end
+				device pnp 2e.2 off end	# COM2
+				device pnp 2e.3 off end	# Parallel port
+				device pnp 2e.4 on	# Environment Controller
+					io  0x60 = 0x0a30
+					irq 0x70 = 9
+					io  0x62 = 0x0a20
+				end
+				device pnp 2e.5 off end	# Keyboard
+				device pnp 2e.6 off end	# Mouse
+				device pnp 2e.7 off end	# GPIO
+				device pnp 2e.a off end	# CIR
+			end
+		end
+
+		device pci 1f.3 on  end # SMBus
+	end
+end

src/mainboard/bostentech/gbyt4/dsdt.asl

@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0 and up
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	// OEM revision
+)
+{
+	#include <soc/intel/baytrail/acpi/platform.asl>
+
+	// global NVS and variables
+	#include <soc/intel/baytrail/acpi/globalnvs.asl>
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <soc/intel/baytrail/acpi/southcluster.asl>
+	}
+
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+	#include "acpi/mainboard.asl"
+}

src/mainboard/bostentech/gbyt4/early_init.c

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <superio/ite/common/ite.h>
+#include <superio/ite/it8728f/it8728f.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, 0x01)
+
+void bootblock_mainboard_early_init(void)
+{
+	/* Enable serial port */
+	ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}

src/mainboard/bostentech/gbyt4/gpio.c

@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+	GPIO_INPUT,			/* GPIO_S0_NC[00] */
+	GPIO_INPUT,			/* GPIO_S0_NC[01] */
+	GPIO_INPUT,			/* GPIO_S0_NC[02] */
+	GPIO_INPUT,			/* GPIO_S0_NC[03] */
+	GPIO_INPUT,			/* GPIO_S0_NC[04] */
+	GPIO_INPUT,			/* GPIO_S0_NC[05] */
+	GPIO_INPUT,			/* GPIO_S0_NC[06] */
+	GPIO_INPUT,			/* GPIO_S0_NC[07] */
+	GPIO_INPUT,			/* GPIO_S0_NC[08] */
+	GPIO_INPUT,			/* GPIO_S0_NC[09] */
+	GPIO_INPUT,			/* GPIO_S0_NC[10] */
+	GPIO_INPUT,			/* GPIO_S0_NC[11] */
+	GPIO_INPUT,			/* GPIO_S0_NC[12] */
+	GPIO_INPUT,			/* GPIO_S0_NC[13] */
+	GPIO_INPUT,			/* GPIO_S0_NC[14] */
+	GPIO_INPUT,			/* GPIO_S0_NC[15] */
+	GPIO_INPUT,			/* GPIO_S0_NC[16] */
+	GPIO_INPUT,			/* GPIO_S0_NC[17] */
+	GPIO_INPUT,			/* GPIO_S0_NC[18] */
+	GPIO_INPUT,			/* GPIO_S0_NC[19] */
+	GPIO_INPUT,			/* GPIO_S0_NC[20] */
+	GPIO_INPUT,			/* GPIO_S0_NC[21] */
+	GPIO_INPUT,			/* GPIO_S0_NC[22] */
+	GPIO_INPUT,			/* GPIO_S0_NC[23] */
+	GPIO_INPUT,			/* GPIO_S0_NC[24] */
+	GPIO_INPUT,			/* GPIO_S0_NC[25] */
+	GPIO_INPUT,			/* GPIO_S0_NC[26] */
+	GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+	GPIO_INPUT,			/* GPIO_S0_SC[000] */
+	GPIO_INPUT,			/* GPIO_S0_SC[001] */
+	GPIO_FUNC1,			/* SATA_LED# */
+	GPIO_FUNC1,			/* PCIE_CLKREQ[0]# */
+	GPIO_FUNC1,			/* PCIE_CLKREQ[1]# */
+	GPIO_FUNC1,			/* PCIE_CLKREQ[2]# */
+	GPIO_FUNC1,			/* PCIE_CLKREQ[3]# */
+	GPIO_INPUT,			/* GPIO_S0_SC[007] */
+	GPIO_INPUT,			/* GPIO_S0_SC[008] */
+	GPIO_INPUT,			/* GPIO_S0_SC[009] */
+	GPIO_INPUT,			/* GPIO_S0_SC[010] */
+	GPIO_INPUT,			/* GPIO_S0_SC[011] */
+	GPIO_INPUT,			/* GPIO_S0_SC[012] */
+	GPIO_INPUT,			/* GPIO_S0_SC[013] */
+	GPIO_INPUT,			/* GPIO_S0_SC[014] */
+	GPIO_INPUT,			/* GPIO_S0_SC[015] */
+	GPIO_INPUT,			/* GPIO_S0_SC[016] */
+	GPIO_INPUT,			/* GPIO_S0_SC[017] */
+	GPIO_INPUT,			/* GPIO_S0_SC[018] */
+	GPIO_INPUT,			/* GPIO_S0_SC[019] */
+	GPIO_INPUT,			/* GPIO_S0_SC[020] */
+	GPIO_INPUT,			/* GPIO_S0_SC[021] */
+	GPIO_INPUT,			/* GPIO_S0_SC[022] */
+	GPIO_INPUT,			/* GPIO_S0_SC[023] */
+	GPIO_INPUT,			/* GPIO_S0_SC[024] */
+	GPIO_INPUT,			/* GPIO_S0_SC[025] */
+	GPIO_INPUT,			/* GPIO_S0_SC[026] */
+	GPIO_INPUT,			/* GPIO_S0_SC[027] */
+	GPIO_INPUT,			/* GPIO_S0_SC[028] */
+	GPIO_INPUT,			/* GPIO_S0_SC[029] */
+	GPIO_INPUT,			/* GPIO_S0_SC[030] */
+	GPIO_INPUT,			/* GPIO_S0_SC[031] */
+	GPIO_INPUT,			/* GPIO_S0_SC[032] */
+	GPIO_INPUT,			/* GPIO_S0_SC[033] */
+	GPIO_INPUT,			/* GPIO_S0_SC[034] */
+	GPIO_INPUT,			/* GPIO_S0_SC[035] */
+	GPIO_INPUT,			/* GPIO_S0_SC[036] */
+	GPIO_INPUT,			/* GPIO_S0_SC[037] */
+	GPIO_INPUT,			/* GPIO_S0_SC[038] */
+	GPIO_INPUT,			/* GPIO_S0_SC[039] */
+	GPIO_INPUT,			/* GPIO_S0_SC[040] */
+	GPIO_INPUT,			/* GPIO_S0_SC[041] */
+	GPIO_FUNC1,			/* ILB_LPC_AD[0] */
+	GPIO_FUNC1,			/* ILB_LPC_AD[1] */
+	GPIO_FUNC1,			/* ILB_LPC_AD[2] */
+	GPIO_FUNC1,			/* ILB_LPC_AD[3] */
+	GPIO_FUNC1,			/* ILB_LPC_FRAME# */
+	GPIO_FUNC1,			/* ILB_LPC_CLK[0] */
+	GPIO_FUNC1,			/* ILB_LPC_CLK[1] */
+	GPIO_FUNC1,			/* ILB_LPC_CLKRUN# */
+	GPIO_FUNC1,			/* ILB_LPC_SERIRQ */
+	GPIO_FUNC1,			/* PCU_SMB_DATA */
+	GPIO_FUNC1,			/* PCU_SMB_CLK */
+	GPIO_FUNC1,			/* PCU_SMB_ALERT# */
+	GPIO_FUNC1,			/* ILB_8254_SPKR */
+	GPIO_INPUT,			/* GPIO_S0_SC[055] */
+	GPIO_INPUT,			/* GPIO_S0_SC[056] */
+	GPIO_INPUT,			/* GPIO_S0_SC[057] */
+	GPIO_INPUT,			/* GPIO_S0_SC[058] */
+	GPIO_INPUT,			/* GPIO_S0_SC[059] */
+	GPIO_INPUT,			/* GPIO_S0_SC[060] */
+	GPIO_INPUT,			/* GPIO_S0_SC[061] */
+	GPIO_INPUT,			/* GPIO_S0_SC[062] */
+	GPIO_INPUT,			/* GPIO_S0_SC[063] */
+	GPIO_INPUT,			/* GPIO_S0_SC[064] */
+	GPIO_INPUT,			/* GPIO_S0_SC[065] */
+	GPIO_INPUT,			/* GPIO_S0_SC[066] */
+	GPIO_INPUT,			/* GPIO_S0_SC[067] */
+	GPIO_INPUT,			/* GPIO_S0_SC[068] */
+	GPIO_INPUT,			/* GPIO_S0_SC[069] */
+	GPIO_INPUT,			/* GPIO_S0_SC[070] */
+	GPIO_INPUT,			/* GPIO_S0_SC[071] */
+	GPIO_INPUT,			/* GPIO_S0_SC[072] */
+	GPIO_INPUT,			/* GPIO_S0_SC[073] */
+	GPIO_INPUT,			/* GPIO_S0_SC[074] */
+	GPIO_INPUT,			/* GPIO_S0_SC[075] */
+	GPIO_INPUT,			/* GPIO_S0_SC[076] */
+	GPIO_INPUT,			/* GPIO_S0_SC[077] */
+	GPIO_INPUT,			/* GPIO_S0_SC[078] */
+	GPIO_INPUT,			/* GPIO_S0_SC[079] */
+	GPIO_INPUT,			/* GPIO_S0_SC[080] */
+	GPIO_INPUT,			/* GPIO_S0_SC[081] */
+	GPIO_INPUT,			/* GPIO_S0_SC[082] */
+	GPIO_INPUT,			/* GPIO_S0_SC[083] */
+	GPIO_INPUT,			/* GPIO_S0_SC[084] */
+	GPIO_INPUT,			/* GPIO_S0_SC[085] */
+	GPIO_INPUT,			/* GPIO_S0_SC[086] */
+	GPIO_INPUT,			/* GPIO_S0_SC[087] */
+	GPIO_INPUT,			/* GPIO_S0_SC[088] */
+	GPIO_INPUT,			/* GPIO_S0_SC[089] */
+	GPIO_INPUT,			/* GPIO_S0_SC[090] */
+	GPIO_INPUT,			/* GPIO_S0_SC[091] */
+	GPIO_INPUT,			/* GPIO_S0_SC[092] */
+	GPIO_INPUT,			/* GPIO_S0_SC[093] */
+	GPIO_INPUT,			/* GPIO_S0_SC[094] */
+	GPIO_INPUT,			/* GPIO_S0_SC[095] */
+	GPIO_INPUT,			/* GPIO_S0_SC[096] */
+	GPIO_INPUT,			/* GPIO_S0_SC[097] */
+	GPIO_INPUT,			/* GPIO_S0_SC[098] */
+	GPIO_INPUT,			/* GPIO_S0_SC[099] */
+	GPIO_INPUT,			/* GPIO_S0_SC[100] */
+	GPIO_INPUT,			/* GPIO_S0_SC[101] */
+	GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+	GPIO_INPUT,			/* GPIO_S5[00] */
+	GPIO_FUNC6,			/* PMC_WAKE_PCIE[1]# */
+	GPIO_FUNC6,			/* PMC_WAKE_PCIE[2]# */
+	GPIO_FUNC6,			/* PMC_WAKE_PCIE[3]# */
+	GPIO_INPUT,			/* GPIO_S5[04] */
+	GPIO_INPUT,			/* GPIO_S5[05] */
+	GPIO_INPUT,			/* GPIO_S5[06] */
+	GPIO_INPUT,			/* GPIO_S5[07] */
+	GPIO_INPUT,			/* GPIO_S5[08] */
+	GPIO_INPUT,			/* GPIO_S5[09] */
+	GPIO_INPUT,			/* GPIO_S5[10] */
+	GPIO_INPUT,			/* GPIO_S5[11] */
+	GPIO_INPUT,			/* GPIO_S5[12] */
+	GPIO_INPUT,			/* GPIO_S5[13] */
+	GPIO_INPUT,			/* GPIO_S5[14] */
+	GPIO_FUNC0,			/* PMC_WAKE_PCIE[0]# */
+	GPIO_FUNC(0, PULL_UP, 20K),	/* PMC_PWRBTN# */
+	GPIO_INPUT,			/* GPIO_S5[17] */
+	GPIO_INPUT,			/* GPIO_S5[18] */
+	GPIO_INPUT,			/* GPIO_S5[19] */
+	GPIO_INPUT,			/* GPIO_S5[20] */
+	GPIO_INPUT,			/* GPIO_S5[21] */
+	GPIO_INPUT,			/* GPIO_S5[22] */
+	GPIO_INPUT,			/* GPIO_S5[23] */
+	GPIO_INPUT,			/* GPIO_S5[24] */
+	GPIO_INPUT,			/* GPIO_S5[25] */
+	GPIO_INPUT,			/* GPIO_S5[26] */
+	GPIO_INPUT,			/* GPIO_S5[27] */
+	GPIO_INPUT,			/* GPIO_S5[28] */
+	GPIO_INPUT,			/* GPIO_S5[29] */
+	GPIO_INPUT,			/* GPIO_S5[30] */
+	GPIO_INPUT,			/* GPIO_S5[31] */
+	GPIO_INPUT,			/* GPIO_S5[32] */
+	GPIO_INPUT,			/* GPIO_S5[33] */
+	GPIO_INPUT,			/* GPIO_S5[34] */
+	GPIO_INPUT,			/* GPIO_S5[35] */
+	GPIO_INPUT,			/* GPIO_S5[36] */
+	GPIO_INPUT,			/* GPIO_S5[37] */
+	GPIO_INPUT,			/* GPIO_S5[38] */
+	GPIO_INPUT,			/* GPIO_S5[39] */
+	GPIO_INPUT,			/* GPIO_S5[40] */
+	GPIO_INPUT,			/* GPIO_S5[41] */
+	GPIO_INPUT,			/* GPIO_S5[42] */
+	GPIO_INPUT,			/* GPIO_S5[43] */
+	GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+};
+
+static struct soc_gpio_config gpio_config = {
+	.ncore = gpncore_gpio_map,
+	.score = gpscore_gpio_map,
+	.ssus  = gpssus_gpio_map,
+	.core_dirq = &core_dedicated_irq,
+	.sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config *mainboard_get_gpios(void)
+{
+	return &gpio_config;
+}

src/mainboard/bostentech/gbyt4/irqroute.c

@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;

src/mainboard/bostentech/gbyt4/irqroute.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+	PCI_DEV_PIRQ_ROUTE(GFX_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(TXE_DEV,  A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+	PCI_DEV_PIRQ_ROUTE(PCU_DEV,  A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+	PIRQ_PIC(A, DISABLE), \
+	PIRQ_PIC(B, DISABLE), \
+	PIRQ_PIC(C, DISABLE), \
+	PIRQ_PIC(D, DISABLE), \
+	PIRQ_PIC(E, DISABLE), \
+	PIRQ_PIC(F, DISABLE), \
+	PIRQ_PIC(G, DISABLE), \
+	PIRQ_PIC(H, DISABLE)

src/mainboard/bostentech/gbyt4/mainboard.c

@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#if CONFIG(VGA_ROM_RUN)
+#include <x86emu/x86emu.h>
+#endif
+#include <acpi/acpi.h>
+#include <arch/interrupt.h>
+#include <smbios.h>
+#include <soc/gpio.h>
+#include <bootstate.h>
+
+void mainboard_suspend_resume(void)
+{
+}
+
+#if CONFIG(VGA_ROM_RUN)
+static int int15_handler(void)
+{
+	int res = 1;
+
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+	       __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+	switch (X86_AX) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video BIOS default
+		 */
+		X86_AX = 0x005f;
+		X86_CX = 0x0001;
+		res = 1;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV
+		 *  bit 2 = EFP (HDMI)
+		 *  bit 3 = LFP (eDP)*
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2
+		 *  bit 6 = EFP2
+		 *  bit 7 = LFP2
+		 */
+		X86_AX = 0x005f;
+		X86_CX = 0x0008;
+		res = 1;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		X86_AX = 0x005f;
+		X86_CX = 0x0003;
+		res = 1;
+		break;
+	case 0x5f70:
+		switch ((X86_CX >> 8) & 0xff) {
+		case 0:
+			/* Get Mux */
+			X86_AX = 0x005f;
+			X86_CX = 0x0000;
+			res = 1;
+			break;
+		case 1:
+			/* Set Mux */
+			X86_AX = 0x005f;
+			X86_CX = 0x0000;
+			res = 1;
+			break;
+		case 2:
+			/* Get SG/Non-SG mode */
+			X86_AX = 0x005f;
+			X86_CX = 0x0000;
+			res = 1;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG,
+			       "Unknown INT15 5f70 function: 0x%02x\n",
+				((X86_CX >> 8) & 0xff));
+			break;
+		}
+		break;
+
+	default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+		break;
+	}
+	return res;
+}
+#endif
+
+static void mainboard_init(struct device *dev)
+{
+
+}
+
+static int mainboard_smbios_data(struct device *dev, int *handle,
+				 unsigned long *current)
+{
+	return 0;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->init = mainboard_init;
+	dev->ops->get_smbios_data = mainboard_smbios_data;
+#if CONFIG(VGA_ROM_RUN)
+		/* Install custom int15 handler for VGA OPROM */
+		mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};

src/mainboard/bostentech/gbyt4/romstage.c

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
+
+void mainboard_fill_mrc_params(struct mrc_params *mp)
+{
+	mp->mainboard.dram_type = DRAM_DDR3L;
+	mp->mainboard.dram_info_location = DRAM_INFO_SPD_SMBUS;
+	mp->mainboard.dram_is_slotted = 1;
+	mp->mainboard.spd_addrs[0] = 0x50; /* Board only has one slot */
+}