soc/intel/fsp_baytrail: convert to using common MP and SMM init
In order to reduce duplication of code use the common MP and SMM initialization flow. Change-Id: I709ea938b720f26b351a1f950593efe077edb997 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/14581 Tested-by: build bot (Jenkins) Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
This commit is contained in:
Aaron Durbin
committed by
Martin Roth
Martin Roth
parent
b04bb65504
commit
2a07a4d62b
@@ -30,32 +30,10 @@
|
||||
#include <soc/msr.h>
|
||||
#include <soc/pattrs.h>
|
||||
#include <soc/ramstage.h>
|
||||
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
|
||||
#include <soc/smm.h>
|
||||
|
||||
static void smm_relocate(void);
|
||||
static void enable_smis(void);
|
||||
|
||||
static struct mp_flight_record mp_steps[] = {
|
||||
MP_FR_BLOCK_APS(smm_relocate, smm_relocate),
|
||||
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
|
||||
/* Wait for APs to finish initialization before proceeding. */
|
||||
MP_FR_BLOCK_APS(NULL, enable_smis),
|
||||
};
|
||||
#else /* CONFIG_HAVE_SMI_HANDLER */
|
||||
static struct mp_flight_record mp_steps[] = {
|
||||
MP_FR_BLOCK_APS(mp_initialize_cpu, mp_initialize_cpu),
|
||||
};
|
||||
#endif
|
||||
|
||||
/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */
|
||||
static int adjust_apic_id(int index, int apic_id)
|
||||
{
|
||||
return 2 * index;
|
||||
}
|
||||
|
||||
/* Core level MSRs */
|
||||
const struct reg_script core_msr_script[] = {
|
||||
static const struct reg_script core_msr_script[] = {
|
||||
/* Dynamic L2 shrink enable and threshold */
|
||||
REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008),
|
||||
/* Disable C1E */
|
||||
@@ -64,29 +42,6 @@ const struct reg_script core_msr_script[] = {
|
||||
REG_SCRIPT_END
|
||||
};
|
||||
|
||||
void baytrail_init_cpus(device_t dev)
|
||||
{
|
||||
struct bus *cpu_bus = dev->link_list;
|
||||
const struct pattrs *pattrs = pattrs_get();
|
||||
struct mp_params mp_params;
|
||||
|
||||
x86_mtrr_check();
|
||||
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
|
||||
mp_params.num_cpus = pattrs->num_cpus,
|
||||
mp_params.parallel_microcode_load = 1,
|
||||
mp_params.adjust_apic_id = adjust_apic_id;
|
||||
mp_params.flight_plan = &mp_steps[0];
|
||||
mp_params.num_records = ARRAY_SIZE(mp_steps);
|
||||
mp_params.microcode_pointer = pattrs->microcode_patch;
|
||||
|
||||
if (mp_init(cpu_bus, &mp_params)) {
|
||||
printk(BIOS_ERR, "MP initialization failure.\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void baytrail_core_init(device_t cpu)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Init BayTrail core.\n");
|
||||
@@ -123,9 +78,8 @@ static const struct cpu_driver driver __cpu_driver = {
|
||||
.id_table = cpu_table,
|
||||
};
|
||||
|
||||
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
|
||||
/*
|
||||
* SMM loading and initialization.
|
||||
* MP and SMM loading initialization.
|
||||
*/
|
||||
|
||||
struct smm_relocation_attrs {
|
||||
@@ -136,32 +90,57 @@ struct smm_relocation_attrs {
|
||||
|
||||
static struct smm_relocation_attrs relo_attrs;
|
||||
|
||||
static void adjust_apic_id_map(struct smm_loader_params *smm_params)
|
||||
static void pre_mp_init(void)
|
||||
{
|
||||
int i;
|
||||
struct smm_runtime *runtime = smm_params->runtime;
|
||||
x86_mtrr_check();
|
||||
|
||||
for (i = 0; i < CONFIG_MAX_CPUS; i++)
|
||||
runtime->apic_id_to_cpu[i] = mp_get_apic_id(i);
|
||||
/* Enable the local cpu apics */
|
||||
setup_lapic();
|
||||
}
|
||||
|
||||
static void asmlinkage cpu_smm_do_relocation(void *arg)
|
||||
static int get_cpu_count(void)
|
||||
{
|
||||
const struct pattrs *pattrs = pattrs_get();
|
||||
|
||||
return pattrs->num_cpus;
|
||||
}
|
||||
|
||||
static void get_smm_info(uintptr_t *perm_smbase, size_t *perm_smsize,
|
||||
size_t *smm_save_state_size)
|
||||
{
|
||||
/* All range registers are aligned to 4KiB */
|
||||
const uint32_t rmask = ~((1 << 12) - 1);
|
||||
|
||||
/* Initialize global tracking state. */
|
||||
relo_attrs.smbase = (uint32_t)smm_region_start();
|
||||
relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
|
||||
relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask;
|
||||
relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
|
||||
|
||||
*perm_smbase = relo_attrs.smbase;
|
||||
*perm_smsize = smm_region_size() - CONFIG_SMM_RESERVED_SIZE;
|
||||
*smm_save_state_size = sizeof(em64t100_smm_state_save_area_t);
|
||||
}
|
||||
|
||||
/* The APIC id space on Bay Trail is sparse. Each id is separated by 2. */
|
||||
static int adjust_apic_id(int index, int apic_id)
|
||||
{
|
||||
return 2 * index;
|
||||
}
|
||||
|
||||
static void get_microcode_info(const void **microcode, int *parallel)
|
||||
{
|
||||
const struct pattrs *pattrs = pattrs_get();
|
||||
|
||||
*microcode = pattrs->microcode_patch;
|
||||
*parallel = 1;
|
||||
}
|
||||
|
||||
static void relocation_handler(int cpu, uintptr_t curr_smbase,
|
||||
uintptr_t staggered_smbase)
|
||||
{
|
||||
msr_t smrr;
|
||||
em64t100_smm_state_save_area_t *smm_state;
|
||||
const struct smm_module_params *p;
|
||||
const struct smm_runtime *runtime;
|
||||
int cpu;
|
||||
|
||||
p = arg;
|
||||
runtime = p->runtime;
|
||||
cpu = p->cpu;
|
||||
|
||||
if (cpu >= CONFIG_MAX_CPUS) {
|
||||
printk(BIOS_CRIT,
|
||||
"Invalid CPU number assigned in SMM stub: %d\n", cpu);
|
||||
return;
|
||||
}
|
||||
|
||||
/* Set up SMRR. */
|
||||
smrr.lo = relo_attrs.smrr_base;
|
||||
@@ -171,105 +150,32 @@ static void asmlinkage cpu_smm_do_relocation(void *arg)
|
||||
smrr.hi = 0;
|
||||
wrmsr(SMRR_PHYS_MASK, smrr);
|
||||
|
||||
/* The relocated handler runs with all CPUs concurrently. Therefore
|
||||
* stagger the entry points adjusting SMBASE downwards by save state
|
||||
* size * CPU num. */
|
||||
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + runtime->smbase);
|
||||
smm_state->smbase = relo_attrs.smbase - cpu * runtime->save_state_size;
|
||||
printk(BIOS_DEBUG, "New SMBASE 0x%08x\n", smm_state->smbase);
|
||||
}
|
||||
|
||||
static int install_relocation_handler(int num_cpus)
|
||||
{
|
||||
const int save_state_size = sizeof(em64t100_smm_state_save_area_t);
|
||||
|
||||
struct smm_loader_params smm_params = {
|
||||
.per_cpu_stack_size = save_state_size,
|
||||
.num_concurrent_stacks = num_cpus,
|
||||
.per_cpu_save_state_size = save_state_size,
|
||||
.num_concurrent_save_states = 1,
|
||||
.handler = (smm_handler_t)&cpu_smm_do_relocation,
|
||||
};
|
||||
|
||||
if (smm_setup_relocation_handler(&smm_params))
|
||||
return -1;
|
||||
|
||||
adjust_apic_id_map(&smm_params);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int install_permanent_handler(int num_cpus)
|
||||
{
|
||||
/* There are num_cpus concurrent stacks and num_cpus concurrent save
|
||||
* state areas. Lastly, set the stack size to the save state size. */
|
||||
int save_state_size = sizeof(em64t100_smm_state_save_area_t);
|
||||
struct smm_loader_params smm_params = {
|
||||
.per_cpu_stack_size = save_state_size,
|
||||
.num_concurrent_stacks = num_cpus,
|
||||
.per_cpu_save_state_size = save_state_size,
|
||||
.num_concurrent_save_states = num_cpus,
|
||||
};
|
||||
const int tseg_size = smm_region_size() - CONFIG_SMM_RESERVED_SIZE;
|
||||
|
||||
printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n",
|
||||
relo_attrs.smbase);
|
||||
|
||||
if (smm_load_module((void *)relo_attrs.smbase, tseg_size, &smm_params))
|
||||
return -1;
|
||||
|
||||
adjust_apic_id_map(&smm_params);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int smm_load_handlers(void)
|
||||
{
|
||||
/* All range registers are aligned to 4KiB */
|
||||
const uint32_t rmask = ~((1 << 12) - 1);
|
||||
const struct pattrs *pattrs = pattrs_get();
|
||||
|
||||
/* Initialize global tracking state. */
|
||||
relo_attrs.smbase = (uint32_t)smm_region_start();
|
||||
relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK;
|
||||
relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask;
|
||||
relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID;
|
||||
|
||||
/* Install handlers. */
|
||||
if (install_relocation_handler(pattrs->num_cpus) < 0) {
|
||||
printk(BIOS_ERR, "Unable to install SMM relocation handler.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (install_permanent_handler(pattrs->num_cpus) < 0) {
|
||||
printk(BIOS_ERR, "Unable to install SMM permanent handler.\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Ensure the SMM handlers hit DRAM before performing first SMI. */
|
||||
wbinvd();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void smm_relocate(void)
|
||||
{
|
||||
|
||||
/* Load relocation and permanent handler. */
|
||||
if (boot_cpu()) {
|
||||
if (smm_load_handlers() < 0) {
|
||||
printk(BIOS_ERR, "Error loading SMM handlers.\n");
|
||||
return;
|
||||
}
|
||||
southcluster_smm_clear_state();
|
||||
}
|
||||
|
||||
/* Relocate SMM space. */
|
||||
smm_initiate_relocation();
|
||||
smm_state = (void *)(SMM_EM64T100_SAVE_STATE_OFFSET + curr_smbase);
|
||||
smm_state->smbase = staggered_smbase;
|
||||
}
|
||||
|
||||
static void enable_smis(void)
|
||||
{
|
||||
southcluster_smm_enable_smi();
|
||||
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
|
||||
southcluster_smm_enable_smi();
|
||||
}
|
||||
|
||||
static const struct mp_ops mp_ops = {
|
||||
.pre_mp_init = pre_mp_init,
|
||||
.get_cpu_count = get_cpu_count,
|
||||
.get_smm_info = get_smm_info,
|
||||
.get_microcode_info = get_microcode_info,
|
||||
.adjust_cpu_apic_entry = adjust_apic_id,
|
||||
.pre_mp_smm_init = southcluster_smm_clear_state,
|
||||
.relocation_handler = relocation_handler,
|
||||
.post_mp_init = enable_smis,
|
||||
};
|
||||
|
||||
void baytrail_init_cpus(device_t dev)
|
||||
{
|
||||
struct bus *cpu_bus = dev->link_list;
|
||||
|
||||
if (mp_init_with_smm(cpu_bus, &mp_ops)) {
|
||||
printk(BIOS_ERR, "MP initialization failure.\n");
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user