Fix the indent and whitespace to match LinuxBIOS standards

Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/southbridge/amd/cs5536/cs5536.c

@@ -102,7 +102,6 @@ uint32_t FlashPort[] = {
 	MDD_LBAR_FLSH3
 };
 
-
 /* ***************************************************************************/
 /* **/
 /* *	pmChipsetInit*/
@@ -110,7 +109,8 @@ uint32_t FlashPort[] = {
 /* *	Program ACPI LBAR and initialize ACPI registers.*/
 /* **/
 /* ***************************************************************************/
-static void pmChipsetInit(void) {
+static void pmChipsetInit(void)
+{
 	uint32_t val = 0;
 	uint16_t port;
 
@@ -142,7 +142,6 @@ static void pmChipsetInit(void) {
 	outl(val, port);
 }
 
-
 /***************************************************************************
  *
  *	ChipsetFlashSetup
@@ -152,7 +151,8 @@ static void pmChipsetInit(void) {
  *	configured (don't call it if you want IDE).
  *
  **************************************************************************/
-static void ChipsetFlashSetup(void){
+static void ChipsetFlashSetup(void)
+{
 	msr_t msr;
 	int i;
 	int numEnabled = 0;
@@ -173,13 +173,15 @@ static void ChipsetFlashSetup(void){
 			else
 				msr.hi &= ~0x00000004;
 			msr.hi |= FlashInitTable[i].fMask;
-			printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
+			printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i],
+				     msr.hi, msr.lo);
 			wrmsr(FlashPort[i], msr);
 
 			/* now write-enable the device */
 			msr = rdmsr(MDD_NORF_CNTRL);
 			msr.lo |= (1 << i);
-			printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
+			printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL,
+				     msr.hi, msr.lo);
 			wrmsr(MDD_NORF_CNTRL, msr);
 
 			/* update the number enabled */
@@ -190,24 +192,26 @@ static void ChipsetFlashSetup(void){
 	printk_debug("ChipsetFlashSetup: Finish\n");
 
 }
+
 /* ***************************************************************************/
 /* **/
 /* *	enable_ide_nand_flash_header */
 /*		Run after VSA init to enable the flash PCI device header */
 /* **/
 /* ***************************************************************************/
-static void enable_ide_nand_flash_header(){
+static void enable_ide_nand_flash_header()
+{
 	/* Tell VSA to use FLASH PCI header. Not IDE header. */
 	outl(0x80007A40, 0xCF8);
 	outl(0xDEADBEEF, 0xCFC);
 }
 
-
 #define RTC_CENTURY 0x32
 #define RTC_DOMA	0x3D
 #define RTC_MONA	0x3E
 
-static void lpc_init(struct southbridge_amd_cs5536_config *sb){
+static void lpc_init(struct southbridge_amd_cs5536_config *sb)
+{
 	msr_t msr;
 
 	if (sb->lpc_serirq_enable) {
@@ -246,14 +250,15 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb){
 	isa_dma_init();
 }
 
-
+static void uarts_init(struct southbridge_amd_cs5536_config *sb)
-static void uarts_init(struct southbridge_amd_cs5536_config *sb){
+{
 	msr_t msr;
 	uint16_t addr;
 	uint32_t gpio_addr;
 	device_t dev;
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+			PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
 	gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
 	gpio_addr &= ~1;	/* clear IO bit */
 	printk_debug("GPIO_ADDR: %08X\n", gpio_addr);
@@ -302,7 +307,8 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
 		outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
 
 		/* Set: GPIO 8 + 9 Pull Up         (0x18) */
-		outl(GPIOL_8_SET | GPIOL_9_SET, gpio_addr + GPIOL_PULLUP_ENABLE);
+		outl(GPIOL_8_SET | GPIOL_9_SET,
+		     gpio_addr + GPIOL_PULLUP_ENABLE);
 
 		/* enable COM1 */
 		/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
@@ -310,8 +316,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
 		msr.hi = 0;
 		wrmsr(MDD_UART1_CONF, msr);
 
-	}
+	} else {
-	else{
 		/* Reset and disable COM1 */
 		printk_err("Not disabling COM1 due to a bug ...\n");
 		/* for now, don't do this! */
@@ -351,7 +356,6 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
 		msr.lo |= addr << 20;
 		wrmsr(MDD_LEG_IO, msr);
 
-
 		/* Set the IRQ */
 		msr = rdmsr(MDD_IRQM_YHIGH);
 		msr.lo |= sb->com2_irq << 28;
@@ -370,7 +374,8 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
 		outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
 
 		/* Set: GPIO 3 + 3 Pull Up         (0x18) */
-		outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE);
+		outl(GPIOL_3_SET | GPIOL_4_SET,
+		     gpio_addr + GPIOL_PULLUP_ENABLE);
 
 		/* enable COM2 */
 		/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
@@ -378,8 +383,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
 		msr.hi = 0;
 		wrmsr(MDD_UART2_CONF, msr);
 
-	}
+	} else {
-	else{
 		/* Reset and disable COM2 */
 		msr = rdmsr(MDD_UART2_CONF);
 		msr.lo = 1;	// reset
@@ -394,8 +398,6 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
 	}
 }
 
-
-
 #define HCCPARAMS		0x08
 #define IPREG04			0xA0
 	#define USB_HCCPW_SET	(1 << 1)
@@ -410,15 +412,14 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
 #define UOCCTL			0x0C
 	#define PADEN_SET		(1 << 7)
 
-
 static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 {
 	uint32_t *bar;
 	msr_t msr;
 	device_t dev;
 
-
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
+			PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
 	if (dev) {
 
 		/* Serial Short Detect Enable */
@@ -438,8 +439,8 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 		*(bar + HCCPARAMS) = 0x00005012;
 	}
 
-
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 	if (dev) {
 		bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
 
@@ -448,8 +449,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 		/* Host or Device? */
 		if (sb->enable_USBP4_device) {
 			*(bar + UOCMUX) |= PMUX_DEVICE;
-		}
+		} else {
-		else{
 			*(bar + UOCMUX) |= PMUX_HOST;
 		}
 
@@ -466,28 +466,34 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 	 * - set PADEN (former OTGPADEN) bit in uoc register
 	 * - set APU bit in uoc register */
 	if (sb->enable_USBP4_device) {
-		dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+		dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+				PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
 		if (dev) {
-			bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+			bar = (uint32_t *) pci_read_config32(dev, 
+					PCI_BASE_ADDRESS_0);
 			*(bar + UDCDEVCTL) |= UDC_SD_SET;
 
 		}
 
-		dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+		dev = dev_find_device(PCI_VENDOR_ID_AMD,
+				PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 		if (dev) {
-			bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
+			bar = (uint32_t *) pci_read_config32(dev,
+					PCI_BASE_ADDRESS_0);
 			*(bar + UOCCTL) |= PADEN_SET;
 			*(bar + UOCCAP) |= APU_SET;
 		}
 	}
 
 	/* Disable virtual PCI UDC and OTG headers */
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+			PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
 	if (dev) {
 		pci_write_config8(dev, 0x7C, 0xDEADBEEF);
 	}
 
-	dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
+	dev = dev_find_device(PCI_VENDOR_ID_AMD, 
+			PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
 	if (dev) {
 		pci_write_config8(dev, 0x7C, 0xDEADBEEF);
 	}
@@ -499,11 +505,13 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
 /*			Called from northbridge init (Pre-VSA). */
 /* **/
 /* ***************************************************************************/
-void chipsetinit (void){
+void chipsetinit(void)
+{
 	device_t dev;
 	msr_t msr;
 	uint32_t msrnum;
-	struct southbridge_amd_cs5536_config  *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
+	struct southbridge_amd_cs5536_config *sb =
+	    (struct southbridge_amd_cs5536_config *)dev->chip_info;
 	struct msrinit *csi;
 
 	outb(P80_CHIPSET_INIT, 0x80);
@@ -520,7 +528,6 @@ void chipsetinit (void){
 		pmChipsetInit();
 	}
 
-
 	/* set hd IRQ */
 	outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
 	outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
@@ -538,7 +545,6 @@ void chipsetinit (void){
 	msr.lo |= GLPCI_CRTL_PPIDE_SET;
 	wrmsr(msrnum, msr);
 
-
 	csi = SB_MASTER_CONF_TABLE;
 	for (; csi->msrnum; csi++) {
 		msr.lo = csi->msr.lo;
@@ -547,7 +553,8 @@ void chipsetinit (void){
 	}
 
 	/*      Flash BAR size Setup */
-	printk_err("%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not ");
+	printk_err("%sDoing ChipsetFlashSetup()\n",
+		   sb->enable_ide_nand_flash == 1 ? "" : "Not ");
 	if (sb->enable_ide_nand_flash == 1)
 		ChipsetFlashSetup();
 
@@ -566,7 +573,8 @@ void chipsetinit (void){
 
 static void southbridge_init(struct device *dev)
 {
-	struct southbridge_amd_cs5536_config  *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
+	struct southbridge_amd_cs5536_config *sb =
+	    (struct southbridge_amd_cs5536_config *)dev->chip_info;
 	int i;
 	/*
 	 * struct device *gpiodev;
@@ -579,11 +587,14 @@ static void southbridge_init(struct device *dev)
 	uarts_init(sb);
 
 	if (sb->enable_gpio_int_route) {
-		vrWrite((VRC_MISCELLANEOUS <<  8) + PCI_INT_AB, (sb->enable_gpio_int_route & 0xFFFF));
+		vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
-		vrWrite((VRC_MISCELLANEOUS <<  8) + PCI_INT_CD, (sb->enable_gpio_int_route >> 16));
+			(sb->enable_gpio_int_route & 0xFFFF));
+		vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
+			(sb->enable_gpio_int_route >> 16));
 	}
 
-	printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
+	printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__,
+		   sb->enable_ide_nand_flash);
 	if (sb->enable_ide_nand_flash == 1) {
 		enable_ide_nand_flash_header();
 	}
@@ -592,13 +603,13 @@ static void southbridge_init(struct device *dev)
 
 	/* disable unwanted virtual PCI devices */
 	for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
-		printk_debug("Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]);
+		printk_debug("Disabling VPCI device: 0x%08X\n",
+			     sb->unwanted_vpci[i]);
 		outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
 		outl(0xDEADBEEF, 0xCFC);
 	}
 }
 
-
 static void southbridge_enable(struct device *dev)
 {
 	printk_err("cs5536: %s: dev is %p\n", __FUNCTION__, dev);

src/southbridge/amd/cs5536/cs5536.h

@@ -203,7 +203,6 @@
 #define MDD_RTC_MONA_IND		(MSR_SB_MDD + 0x056)
 #define MDD_RTC_CENTURY_OFFSET	(MSR_SB_MDD + 0x057)
 
-
 /* ***********************************************************/
 /*	LBUS Device Equates - */
 /* ***********************************************************/
@@ -321,7 +320,6 @@
 #define GPIOH_30_CLEAR	(1 << 30)
 #define GPIOH_31_CLEAR	(1 << 31)
 
-
 /*	GPIO LOW Bank Bit Registers*/
 #define GPIOL_OUTPUT_VALUE			(0x00)
 #define GPIOL_OUTPUT_ENABLE			(0x04)
@@ -439,7 +437,6 @@
 #define PM_AWKD		(0x50)
 #define PM_SSC		(0x54)
 
-
 /* FLASH device macros */
 #define FLASH_TYPE_NONE	0	/* No flash device installed */
 #define FLASH_TYPE_NAND 1	/* NAND device */
@@ -467,5 +464,4 @@
 #define FLASH_IO_128B		0x0000FF80
 #define FLASH_IO_256B		0x0000FF00
 
-
 #endif				/* _CS5536_H */

src/southbridge/amd/cs5536/cs5536_early_setup.c

@@ -33,9 +33,11 @@ static void cs5536_setup_extmsr(void)
 	/* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
 	msr.hi = msr.lo = 0x00000000;
 	if (CS5536_GLINK_PORT_NUM <= 4) {
-		msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
+		msr.lo = CS5536_DEV_NUM << 
+			(unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
 	} else {
-		msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
+		msr.hi = CS5536_DEV_NUM << 
+			(unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
 	}
 	wrmsr(GLPCI_ExtMSR, msr);
 }
@@ -96,9 +98,10 @@ static void cs5536_setup_power_button(void)
 	outl(0x40020000, PMS_IO_BASE + 0x40);
 
 	/* setup GPIO24, it is the external signal for 5536 vsb_work_aux
-	; which controls all voltage rails except Vstandby & Vmem.
+	 * which controls all voltage rails except Vstandby & Vmem.
-	; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
+	 * We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
-	; If GPIO24 is not enabled then soft-off will not work. */
+	 * If GPIO24 is not enabled then soft-off will not work. 
+	 */
 	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
 	outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
 
@@ -123,8 +126,9 @@ static void cs5536_setup_gpio(void)
 static void cs5536_disable_internal_uart(void)
 {
 	msr_t msr;
-	/* ; The UARTs default to enabled.
+	/* The UARTs default to enabled.
-	; Disable and reset them and configure them later. (SIO init) */
+	 * Disable and reset them and configure them later. (SIO init) 
+	 */
 	msr = rdmsr(MDD_UART1_CONF);
 	msr.lo = 1;		// reset
 	wrmsr(MDD_UART1_CONF, msr);
@@ -149,7 +153,6 @@ static void cs5536_setup_cis_mode(void)
 	wrmsr(GLPCI_SB_CTRL, msr);
 }
 
-
 /* see page 412 of the cs5536 companion book */
 static void cs5536_setup_onchipuart(void)
 {

src/southbridge/amd/cs5536/cs5536_early_smbus.c

@@ -24,7 +24,6 @@
 #define SMBUS_WAIT_UNTIL_DONE_TIMEOUT  -3
 #define SMBUS_TIMEOUT (1000)
 
-
 /* initialization for SMBus Controller */
 static void cs5536_enable_smbus(void)
 {
@@ -43,8 +42,8 @@ static void smbus_delay(void)
 	/* inb(0x80); */
 }
 
-
+static int smbus_wait(unsigned smbus_io_base)
-static int smbus_wait(unsigned smbus_io_base) {
+{
 	unsigned long loops = SMBUS_TIMEOUT;
 	unsigned char val;
 
@@ -113,7 +112,8 @@ static int smbus_ack(unsigned smbus_io_base, int state)
 	return 0;
 }
 
-static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
+static int smbus_send_slave_address(unsigned smbus_io_base,
+				    unsigned char device)
 {
 	unsigned char val;
 
@@ -122,8 +122,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
 
 	/* check for bus conflict and NACK */
 	val = inb(smbus_io_base + SMB_STS);
-	if (((val & SMB_STS_BER)	!= 0) ||
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
-		((val & SMB_STS_NEGACK) != 0)) {
 		/* printk_debug("SEND SLAVE ERROR (%x)\n", val); */
 		return SMBUS_ERROR;
 	}
@@ -139,8 +138,7 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
 
 	/* check for bus conflict and NACK */
 	val = inb(smbus_io_base + SMB_STS);
-	if (((val & SMB_STS_BER)	!= 0) ||
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
-		((val & SMB_STS_NEGACK) != 0))
 		return SMBUS_ERROR;
 
 	return smbus_wait(smbus_io_base);
@@ -151,7 +149,9 @@ static unsigned char smbus_get_result(unsigned smbus_io_base)
 	return inb(smbus_io_base + SMB_SDA);
 }
 
-static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
+static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
+					unsigned char device,
+					unsigned char address)
 {
 	unsigned char error = 0;
 
@@ -194,7 +194,6 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char de
 
 	return smbus_get_result(smbus_io_base);
 
-
       err:
 	print_debug("SMBUS READ ERROR:");
 	print_debug_hex8(error);
@@ -212,4 +211,3 @@ static inline int smbus_read_byte(unsigned device, unsigned address)
 {
 	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
 }
-

src/southbridge/amd/cs5536/cs5536_smbus2.h

@@ -62,13 +62,13 @@
 #define SMBUS_TIMEOUT (100*1000*10)
 #define SMBUS_STATUS_MASK 0xfbff
 
-
 static void smbus_delay(void)
 {
 	inb(0x80);
 }
 
-static int smbus_wait(unsigned smbus_io_base) {
+static int smbus_wait(unsigned smbus_io_base)
+{
 	unsigned long loops = SMBUS_TIMEOUT;
 	unsigned char val;
 
@@ -87,7 +87,8 @@ static int smbus_wait(unsigned smbus_io_base) {
 	return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
 }
 
-static int smbus_write(unsigned smbus_io_base, unsigned char byte) {
+static int smbus_write(unsigned smbus_io_base, unsigned char byte)
+{
 
 	outb(byte, smbus_io_base + SMB_SDA);
 	return smbus_wait(smbus_io_base);
@@ -159,7 +160,8 @@ static int smbus_ack(unsigned smbus_io_base, int state)
 	return 0;
 }
 
-static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
+static int smbus_send_slave_address(unsigned smbus_io_base,
+				    unsigned char device)
 {
 	unsigned char val;
 
@@ -168,8 +170,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
 
 	/* check for bus conflict and NACK */
 	val = inb(smbus_io_base + SMB_STS);
-	if (((val & SMB_STS_BER)    != 0) ||
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
-	    ((val & SMB_STS_NEGACK) != 0)) {
 		printk_debug("SEND SLAVE ERROR (%x)\n", val);
 		return SMBUS_ERROR;
 	}
@@ -185,8 +186,7 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
 
 	/* check for bus conflict and NACK */
 	val = inb(smbus_io_base + SMB_STS);
-	if (((val & SMB_STS_BER)    != 0) ||
+	if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
-	    ((val & SMB_STS_NEGACK) != 0))
 		return SMBUS_ERROR;
 
 	return smbus_wait(smbus_io_base);
@@ -263,7 +263,8 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
 }
 
 static unsigned short do_smbus_read_word(unsigned smbus_io_base,
-		unsigned char device, unsigned char address)
+					 unsigned char device,
+					 unsigned char address)
 {
 	unsigned short val = 0;
 	_doread(smbus_io_base, device, address, (unsigned char *)&val,
@@ -272,7 +273,8 @@ static unsigned short do_smbus_read_word(unsigned smbus_io_base,
 }
 
 static int _dowrite(unsigned smbus_io_base, unsigned char device,
-		unsigned char address, unsigned char *data, int count) {
+		    unsigned char address, unsigned char *data, int count)
+{
 
 	int ret;
 
@@ -302,7 +304,6 @@ static int _dowrite(unsigned smbus_io_base, unsigned char device,
 	return -1;
 }
 
-
 static int do_smbus_write_byte(unsigned smbus_io_base, unsigned char device,
 			       unsigned char address, unsigned char data)
 {
@@ -310,8 +311,9 @@ static int do_smbus_write_byte(unsigned smbus_io_base, unsigned char device,
 			(unsigned char *)&data, 1);
 }
 
-static int do_smbus_write_word(unsigned smbus_io_base, unsigned char device, unsigned char address,
+static int do_smbus_write_word(unsigned smbus_io_base, unsigned char device,
-			       unsigned short data)
+			       unsigned char address, unsigned short data)
 {
-	return _dowrite(smbus_io_base, device ,address, (unsigned char *) &data, 2);
+	return _dowrite(smbus_io_base, device, address, (unsigned char *)&data,
+			2);
 }