sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

factor out cpu power management base into a separate file. And fix a bug in

Browse Source 
model_1067x

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-12-11 22:14:44 +00:00
committed by Stefan Reinauer
parent 2b9070a610
commit 2a27b20226
6 changed files with 38 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/cpu/intel/model_1067x/model_1067x_init.c
View File

@ -28,6 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
@ -98,8 +99,6 @@ static void enable_vmx(void)
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
#define PMB0_BASE 0x580
#define PMB1_BASE 0x800
#define CST_RANGE 2
static void configure_c_states(void)
{

5
src/cpu/intel/model_106cx/model_106cx_init.c
View File

@ -26,6 +26,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
@ -82,9 +83,7 @@ static void enable_vmx(void)
#define PMG_CST_CONFIG_CONTROL 0xe2
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
#define PMB0 0x510 /* analogous to P_BLK in cpu.asl */
#define PMB1 0x0 /* IO port that triggers SMI once cores are in the same state.
See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4] */
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
{

10
src/cpu/intel/model_6ex/model_6ex_init.c
View File

@ -29,6 +29,7 @@
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <usbdebug.h>
@ -80,15 +81,6 @@ static void enable_vmx(void)
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
/* MWAIT coordination I/O base address. This must match
* the \_PR_.CPU0 PM base address.
*/
#define PMB0_BASE 0x510
/* PMB1: I/O port that triggers SMI once cores are in the same state.
* See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
*/
#define PMB1_BASE 0x800
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
{

10
src/cpu/intel/model_6fx/model_6fx_init.c
View File

@ -28,6 +28,7 @@
#include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h>
#include <cpu/intel/microcode.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/hyperthreading.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
@ -94,15 +95,6 @@ static void enable_vmx(void)
#define PMG_IO_BASE_ADDR 0xe3
#define PMG_IO_CAPTURE_ADDR 0xe4
/* MWAIT coordination I/O base address. This must match
* the \_PR_.CPU0 PM base address.
*/
#define PMB0_BASE 0x510
/* PMB1: I/O port that triggers SMI once cores are in the same state.
* See CSM Trigger, at PMG_CST_CONFIG_CONTROL[6:4]
*/
#define PMB1_BASE 0x800
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
{

3
src/cpu/intel/speedstep/acpi.c
View File

@ -26,6 +26,7 @@
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <cpu/intel/acpi.h>
#include <cpu/intel/speedstep.h>
#include <device/device.h>
// XXX: PSS table values for power consumption are for Merom only
@ -64,7 +65,7 @@ static int get_fsb(void)
void generate_cpu_entries(void)
{
int len_pr, len_ps;
int coreID, cpuID, pcontrol_blk=0x510, plen=6;
int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
msr_t msr;
int totalcores = determine_total_number_of_cores();
int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;