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Trivial. Spelling check.

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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao
2010-10-10 15:18:53 +00:00
committed by Zheng Bao
parent 115c5b9824
commit 2a5101aba4
10 changed files with 18 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/southbridge/amd/sb600/sb600_hda.c
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@@ -53,7 +53,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
dword &= mask; dword &= mask;
} while ((dword != val) && --count); } while ((dword != val) && --count);
/* Timeout occured */ /* Timeout occurred */
if (!count) if (!count)
return -1; return -1;
return 0; return 0;
@@ -169,7 +169,7 @@ static u32 find_verb(u32 viddid, u32 ** verb)
} }
/** /**
* Wait 50usec for for the codec to indicate it is ready * Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative * no response would imply that the codec is non-operative
*/ */
static int wait_for_ready(u32 base) static int wait_for_ready(u32 base)
@@ -190,7 +190,7 @@ static int wait_for_ready(u32 base)
} }
/** /**
* Wait 50usec for for the codec to indicate that it accepted * Wait 50usec for the codec to indicate that it accepted
* the previous command. No response would imply that the code * the previous command. No response would imply that the code
* is non-operative * is non-operative
*/ */

4
src/southbridge/amd/sb600/sb600_sata.c
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@@ -39,7 +39,7 @@ static int sata_drive_detect(int portnum, u16 iobar)
if (byte != (0xA0 + 0x10 * (portnum % 2))) { if (byte != (0xA0 + 0x10 * (portnum % 2))) {
/* This will happen at the first iteration of this loop /* This will happen at the first iteration of this loop
* if the first SATA port is unpopulated and the * if the first SATA port is unpopulated and the
* second SATA port is poulated. * second SATA port is populated.
*/ */
printk(BIOS_DEBUG, "drive no longer selected after %i ms, " printk(BIOS_DEBUG, "drive no longer selected after %i ms, "
"retrying init\n", i * 10); "retrying init\n", i * 10);
@@ -83,7 +83,7 @@ static void sata_init(struct device *dev)
byte = 0x6 << 2; byte = 0x6 << 2;
pci_write_config8(sm_dev, 0xaf, byte); pci_write_config8(sm_dev, 0xaf, byte);
/* get base addresss */ /* get base address */
sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;

2
src/southbridge/amd/sb600/sb600_sm.c
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@@ -338,7 +338,7 @@ static void sb600_sm_set_resources(struct device *dev)
pci_dev_set_resources(dev); pci_dev_set_resources(dev);
/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
byte = pm_ioread(0x52); byte = pm_ioread(0x52);
byte |= 1 << 6; byte |= 1 << 6;
pm_iowrite(0x52, byte); pm_iowrite(0x52, byte);

2
src/southbridge/amd/sb600/sb600_usb.c
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@@ -96,7 +96,7 @@ static void usb_init2(struct device *dev)
usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0); printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
/* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ /* RPR5.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00; dword = 0x00020F00;
write32(usb2_bar0 + 0xC0, dword); write32(usb2_bar0 + 0xC0, dword);

4
src/southbridge/amd/sb700/sb700_early_setup.c
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@@ -63,7 +63,7 @@ static u8 set_sb700_revision(void)
rev = 0x11; /* A11 */ rev = 0x11; /* A11 */
else if (enable_14Mhz == 0x1) { else if (enable_14Mhz == 0x1) {
/* This happens, if does, only once. So later if we need to get /* This happens, if does, only once. So later if we need to get
* the rivision ID, we don't have to make such a big function. * the revision ID, we don't have to make such a big function.
* We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */ * We just get reg 0x8 in smbus dev. 0x39 is A11, 0x3A is A12. */
rev = 0x12; rev = 0x12;
byte = pci_read_config8(dev, 0x40); byte = pci_read_config8(dev, 0x40);
@@ -549,7 +549,7 @@ static void sb700_pci_cfg(void)
/* LPC Device, BDF:0-20-3 */ /* LPC Device, BDF:0-20-3 */
/* The code below is ported from old chipset. It is not /* The code below is ported from old chipset. It is not
* metioned in RPR. But I keep them. The registers and the * mentioned in RPR. But I keep them. The registers and the
* comments are compatible. */ * comments are compatible. */
dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0); dev = pci_locate_device(PCI_ID(0x1002, 0x439D), 0);
/* Enabling LPC DMA function. */ /* Enabling LPC DMA function. */

4
src/southbridge/amd/sb700/sb700_hda.c
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@@ -91,7 +91,7 @@ no_codec:
} }
/** /**
* Wait 50usec for for the codec to indicate it is ready * Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative * no response would imply that the codec is non-operative
*/ */
static int wait_for_ready(u32 base) static int wait_for_ready(u32 base)
@@ -112,7 +112,7 @@ static int wait_for_ready(u32 base)
} }
/** /**
* Wait 50usec for for the codec to indicate that it accepted * Wait 50usec for the codec to indicate that it accepted
* the previous command. No response would imply that the code * the previous command. No response would imply that the code
* is non-operative * is non-operative
*/ */

2
src/southbridge/amd/sb700/sb700_lpc.c
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@@ -108,7 +108,7 @@ static void sb700_lpc_set_resources(struct device *dev)
/** /**
* @brief Enable resources for children devices * @brief Enable resources for children devices
* *
* @param dev the device whos children's resources are to be enabled * @param dev the device whose children's resources are to be enabled
* *
*/ */
static void sb700_lpc_enable_childrens_resources(device_t dev) static void sb700_lpc_enable_childrens_resources(device_t dev)

2
src/southbridge/amd/sb700/sb700_sata.c
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@@ -111,7 +111,7 @@ static void sata_init(struct device *dev)
/* get rev_id */ /* get rev_id */
rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; rev_id = pci_read_config8(sm_dev, 0x08) - 0x28;
/* get base addresss */ /* get base address */
sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF; sata_bar5 = pci_read_config32(dev, 0x24) & ~0x3FF;
sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7; sata_bar0 = pci_read_config16(dev, 0x10) & ~0x7;
sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3; sata_bar1 = pci_read_config16(dev, 0x14) & ~0x3;

4
src/southbridge/amd/sb700/sb700_sm.c
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@@ -206,7 +206,7 @@ static void sm_init(device_t dev)
/* 4.14:Enabling Requester ID for upstream traffic. */ /* 4.14:Enabling Requester ID for upstream traffic. */
abcfg_reg(0x98, 1 << 16, 1 << 16); abcfg_reg(0x98, 1 << 16, 1 << 16);
/* 9.2: Enableing IDE Data Bus DD7 Pull Down Resistor */ /* 9.2: Enabling IDE Data Bus DD7 Pull Down Resistor */
byte = pm2_ioread(0xE5); byte = pm2_ioread(0xE5);
byte |= 1 << 2; byte |= 1 << 2;
pm2_iowrite(0xE5, byte); pm2_iowrite(0xE5, byte);
@@ -345,7 +345,7 @@ static void sb700_sm_set_resources(struct device *dev)
pci_dev_set_resources(dev); pci_dev_set_resources(dev);
/* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridage */ /* rpr2.14: Make HPET MMIO decoding controlled by the memory enable bit in command register of LPC ISA bridge */
byte = pm_ioread(0x52); byte = pm_ioread(0x52);
byte |= 1 << 6; byte |= 1 << 6;
pm_iowrite(0x52, byte); pm_iowrite(0x52, byte);

6
src/southbridge/amd/sb700/sb700_usb.c
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@@ -83,7 +83,7 @@ static void usb_init2(struct device *dev)
usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF; usb2_bar0 = pci_read_config32(dev, 0x10) & ~0xFF;
printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0); printk(BIOS_INFO, "usb2_bar0=0x%x\n", usb2_bar0);
/* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistence */ /* RPR6.4 Enables the USB PHY auto calibration resister to match 45ohm resistance */
dword = 0x00020F00; dword = 0x00020F00;
write32(usb2_bar0 + 0xC0, dword); write32(usb2_bar0 + 0xC0, dword);
@@ -105,8 +105,8 @@ static void usb_init2(struct device *dev)
pci_write_config32(dev, 0x50, dword); pci_write_config32(dev, 0x50, dword);
#endif #endif
/* RPR6.13 Enabling Fix for EHCI Controller Dirver Yellow Sign Issue */ /* RPR6.13 Enabling Fix for EHCI Controller Driver Yellow Sign Issue */
/* RPR says it is just for A12. CIMM sets it when it is above A11. */ /* RPR says it is just for A12. CIMx sets it when it is above A11. */
dword = pci_read_config32(dev, 0x50); dword = pci_read_config32(dev, 0x50);
dword |= (1 << 20); dword |= (1 << 20);
pci_write_config32(dev, 0x50, dword); pci_write_config32(dev, 0x50, dword);