pci_ids.h: Make Denverton IDs consistent with other Intel SoCs
Align Denverton PCI ID define names with other Intel SoCs. Also, update the names in SoC code accordingly. Signed-off-by: Jeff Daly <jeffd@silicom-usa.com> Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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@@ -2755,38 +2755,38 @@
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#define PCI_DEVICE_ID_INTEL_PCIE_PC 0x3599
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/* Intel Denverton (Atom C3000 family) */
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#define PCI_DEVICE_ID_INTEL_DENVERTON_SA 0x1980
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#define PCI_DEVICE_ID_INTEL_DENVERTONAD_SA 0x1995
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#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP0 0x19a4
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#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP1 0x19a5
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#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP2 0x19a6
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#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP3 0x19a7
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#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP4 0x19a8
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#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP5 0x19a9
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#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP6 0x19aa
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#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP7 0x19ab
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#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS 0x19ac
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#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1 0x19b2
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#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2 0x19c2
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#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI 0x19d0
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#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_1 0x19d1
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#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_2 0x19d2
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#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_1 0x19d3
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#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_2 0x19d4
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#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT 0x19d5
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#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_3 0x19d6
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#define PCI_DEVICE_ID_INTEL_DENVERTON_HSUART 0x19d8
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#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_1 0x19e5
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#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_2 0x19e6
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#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT 0x19e8
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#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_3 0x19e9
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#define PCI_DEVICE_ID_INTEL_DENVERTON_EMMC 0x19db
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#define PCI_DEVICE_ID_INTEL_DENVERTON_LPC 0x19dc
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#define PCI_DEVICE_ID_INTEL_DENVERTON_P2SB 0x19dd
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#define PCI_DEVICE_ID_INTEL_DENVERTON_PMC 0x19de
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#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY 0x19df
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#define PCI_DEVICE_ID_INTEL_DENVERTON_SPI 0x19e0
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#define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB 0x19e1
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#define PCI_DEVICE_ID_INTEL_DNV_SA 0x1980
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#define PCI_DEVICE_ID_INTEL_DNVAD_SA 0x1995
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#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP0 0x19a4
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#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP1 0x19a5
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#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP2 0x19a6
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#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP3 0x19a7
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#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP4 0x19a8
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#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP5 0x19a9
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#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP6 0x19aa
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#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP7 0x19ab
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#define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19ac
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#define PCI_DEVICE_ID_INTEL_DNV_SATA_AHCI_1 0x19b2
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#define PCI_DEVICE_ID_INTEL_DNV_SATA_AHCI_2 0x19c2
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#define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
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#define PCI_DEVICE_ID_INTEL_DNV_LAN_1 0x19d1
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#define PCI_DEVICE_ID_INTEL_DNV_LAN_2 0x19d2
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#define PCI_DEVICE_ID_INTEL_DNV_ME_HECI_1 0x19d3
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#define PCI_DEVICE_ID_INTEL_DNV_ME_HECI_2 0x19d4
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#define PCI_DEVICE_ID_INTEL_DNV_ME_KT 0x19d5
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#define PCI_DEVICE_ID_INTEL_DNV_ME_HECI_3 0x19d6
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#define PCI_DEVICE_ID_INTEL_DNV_HSUART 0x19d8
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#define PCI_DEVICE_ID_INTEL_DNV_IE_HECI_1 0x19e5
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#define PCI_DEVICE_ID_INTEL_DNV_IE_HECI_2 0x19e6
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#define PCI_DEVICE_ID_INTEL_DNV_IE_KT 0x19e8
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#define PCI_DEVICE_ID_INTEL_DNV_IE_HECI_3 0x19e9
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#define PCI_DEVICE_ID_INTEL_DNV_EMMC 0x19db
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#define PCI_DEVICE_ID_INTEL_DNV_LPC 0x19dc
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#define PCI_DEVICE_ID_INTEL_DNV_P2SB 0x19dd
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#define PCI_DEVICE_ID_INTEL_DNV_PMC 0x19de
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#define PCI_DEVICE_ID_INTEL_DNV_SMBUS_LEGACY 0x19df
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#define PCI_DEVICE_ID_INTEL_DNV_SPI 0x19e0
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#define PCI_DEVICE_ID_INTEL_DNV_TRACEHUB 0x19e1
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/* Intel Ibex Peak (5 Series Chipset and 3400 Series Chipset) */
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#define PCI_DID_INTEL_IBEXPEAK_LPC_P55 0x3b02
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