pci_ids.h: Make Denverton IDs consistent with other Intel SoCs

Align Denverton PCI ID define names with other Intel SoCs. Also,
update the names in SoC code accordingly.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Change-Id: Id4b4d971ef8f4b3ec5920209d345edbbcfae4dec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/include/device/pci_ids.h

@@ -2755,38 +2755,38 @@
 #define PCI_DEVICE_ID_INTEL_PCIE_PC	0x3599
 
 /* Intel Denverton (Atom C3000 family) */
-#define PCI_DEVICE_ID_INTEL_DENVERTON_SA		0x1980
-#define PCI_DEVICE_ID_INTEL_DENVERTONAD_SA		0x1995
-#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP0		0x19a4
-#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP1		0x19a5
-#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP2		0x19a6
-#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP3		0x19a7
-#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP4		0x19a8
-#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP5		0x19a9
-#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP6		0x19aa
-#define PCI_DEVICE_ID_INTEL_DENVERTON_PCIE_RP7		0x19ab
-#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS		0x19ac
-#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1	0x19b2
-#define PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2	0x19c2
-#define PCI_DEVICE_ID_INTEL_DENVERTON_XHCI		0x19d0
-#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_1		0x19d1
-#define PCI_DEVICE_ID_INTEL_DENVERTON_LAN_2		0x19d2
-#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_1		0x19d3
-#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_2		0x19d4
-#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT		0x19d5
-#define PCI_DEVICE_ID_INTEL_DENVERTON_ME_HECI_3		0x19d6
-#define PCI_DEVICE_ID_INTEL_DENVERTON_HSUART		0x19d8
-#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_1		0x19e5
-#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_2		0x19e6
-#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT		0x19e8
-#define PCI_DEVICE_ID_INTEL_DENVERTON_IE_HECI_3		0x19e9
-#define PCI_DEVICE_ID_INTEL_DENVERTON_EMMC		0x19db
-#define PCI_DEVICE_ID_INTEL_DENVERTON_LPC		0x19dc
-#define PCI_DEVICE_ID_INTEL_DENVERTON_P2SB		0x19dd
-#define PCI_DEVICE_ID_INTEL_DENVERTON_PMC		0x19de
-#define PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY	0x19df
-#define PCI_DEVICE_ID_INTEL_DENVERTON_SPI		0x19e0
-#define PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB		0x19e1
+#define PCI_DEVICE_ID_INTEL_DNV_SA		0x1980
+#define PCI_DEVICE_ID_INTEL_DNVAD_SA		0x1995
+#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP0	0x19a4
+#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP1	0x19a5
+#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP2	0x19a6
+#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP3	0x19a7
+#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP4	0x19a8
+#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP5	0x19a9
+#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP6	0x19aa
+#define PCI_DEVICE_ID_INTEL_DNV_PCIE_RP7	0x19ab
+#define PCI_DEVICE_ID_INTEL_DNV_SMBUS		0x19ac
+#define PCI_DEVICE_ID_INTEL_DNV_SATA_AHCI_1	0x19b2
+#define PCI_DEVICE_ID_INTEL_DNV_SATA_AHCI_2	0x19c2
+#define PCI_DEVICE_ID_INTEL_DNV_XHCI		0x19d0
+#define PCI_DEVICE_ID_INTEL_DNV_LAN_1		0x19d1
+#define PCI_DEVICE_ID_INTEL_DNV_LAN_2		0x19d2
+#define PCI_DEVICE_ID_INTEL_DNV_ME_HECI_1	0x19d3
+#define PCI_DEVICE_ID_INTEL_DNV_ME_HECI_2	0x19d4
+#define PCI_DEVICE_ID_INTEL_DNV_ME_KT		0x19d5
+#define PCI_DEVICE_ID_INTEL_DNV_ME_HECI_3	0x19d6
+#define PCI_DEVICE_ID_INTEL_DNV_HSUART		0x19d8
+#define PCI_DEVICE_ID_INTEL_DNV_IE_HECI_1	0x19e5
+#define PCI_DEVICE_ID_INTEL_DNV_IE_HECI_2	0x19e6
+#define PCI_DEVICE_ID_INTEL_DNV_IE_KT		0x19e8
+#define PCI_DEVICE_ID_INTEL_DNV_IE_HECI_3	0x19e9
+#define PCI_DEVICE_ID_INTEL_DNV_EMMC		0x19db
+#define PCI_DEVICE_ID_INTEL_DNV_LPC		0x19dc
+#define PCI_DEVICE_ID_INTEL_DNV_P2SB		0x19dd
+#define PCI_DEVICE_ID_INTEL_DNV_PMC		0x19de
+#define PCI_DEVICE_ID_INTEL_DNV_SMBUS_LEGACY	0x19df
+#define PCI_DEVICE_ID_INTEL_DNV_SPI		0x19e0
+#define PCI_DEVICE_ID_INTEL_DNV_TRACEHUB	0x19e1
 
 /* Intel Ibex Peak (5 Series Chipset and 3400 Series Chipset) */
 #define PCI_DID_INTEL_IBEXPEAK_LPC_P55			0x3b02

src/soc/intel/common/block/smbus/smbus.c

@@ -91,7 +91,7 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_ADP_P_SMBUS,
 	PCI_DEVICE_ID_INTEL_ADP_S_SMBUS,
 	PCI_DEVICE_ID_INTEL_ADP_M_SMBUS,
-	PCI_DEVICE_ID_INTEL_DENVERTON_SMBUS_LEGACY,
+	PCI_DEVICE_ID_INTEL_DNV_SMBUS_LEGACY,
 	0
 };
 

src/soc/intel/denverton_ns/csme_ie_kt.c

@@ -59,8 +59,8 @@ static struct device_operations csme_ie_kt_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	PCI_DEVICE_ID_INTEL_DENVERTON_ME_KT,
-	PCI_DEVICE_ID_INTEL_DENVERTON_IE_KT,
+	PCI_DEVICE_ID_INTEL_DNV_ME_KT,
+	PCI_DEVICE_ID_INTEL_DNV_IE_KT,
 	0
 };
 

src/soc/intel/denverton_ns/lpc.c

@@ -535,7 +535,7 @@ static struct device_operations device_ops = {
 static const struct pci_driver lpc_driver __pci_driver = {
 	.ops = &device_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_DENVERTON_LPC,
+	.device = PCI_DEVICE_ID_INTEL_DNV_LPC,
 };
 
 static void finalize_chipset(void *unused)

src/soc/intel/denverton_ns/npk.c

@@ -31,5 +31,5 @@ static struct device_operations pmc_ops = {
 static const struct pci_driver pch_pmc __pci_driver = {
 	.ops = &pmc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_DENVERTON_TRACEHUB,
+	.device = PCI_DEVICE_ID_INTEL_DNV_TRACEHUB,
 };

src/soc/intel/denverton_ns/pmc.c

@@ -106,5 +106,5 @@ static struct device_operations pmc_ops = {
 static const struct pci_driver pch_pmc __pci_driver = {
 	.ops = &pmc_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_DENVERTON_PMC,
+	.device = PCI_DEVICE_ID_INTEL_DNV_PMC,
 };

src/soc/intel/denverton_ns/sata.c

@@ -56,8 +56,8 @@ static struct device_operations sata_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
-	PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_1,
-	PCI_DEVICE_ID_INTEL_DENVERTON_SATA_AHCI_2,
+	PCI_DEVICE_ID_INTEL_DNV_SATA_AHCI_1,
+	PCI_DEVICE_ID_INTEL_DNV_SATA_AHCI_2,
 	0
 };
 

src/soc/intel/denverton_ns/systemagent.c

@@ -333,8 +333,8 @@ static struct device_operations systemagent_ops = {
 
 /* IDs for System Agent device of Intel Denverton SoC */
 static const unsigned short systemagent_ids[] = {
-	PCI_DEVICE_ID_INTEL_DENVERTON_SA,
-	PCI_DEVICE_ID_INTEL_DENVERTONAD_SA,
+	PCI_DEVICE_ID_INTEL_DNV_SA,
+	PCI_DEVICE_ID_INTEL_DNVAD_SA,
 	0
 };
 

src/soc/intel/denverton_ns/uart.c

@@ -45,7 +45,7 @@ static struct device_operations uart_ops = {
 static const struct pci_driver uart_driver __pci_driver = {
 	.ops = &uart_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_DENVERTON_HSUART
+	.device = PCI_DEVICE_ID_INTEL_DNV_HSUART
 };
 
 static void hide_hsuarts(void)

src/soc/intel/denverton_ns/xhci.c

@@ -32,5 +32,5 @@ static struct device_operations usb_xhci_ops = {
 static const struct pci_driver pch_usb_xhci __pci_driver = {
 	.ops = &usb_xhci_ops,
 	.vendor = PCI_VENDOR_ID_INTEL,
-	.device = PCI_DEVICE_ID_INTEL_DENVERTON_XHCI,
+	.device = PCI_DEVICE_ID_INTEL_DNV_XHCI,
 };