Fixes for Nokia IP530 and associated drivers.
Signed-off-by: Marc Bertens <mbertens@xs4all.nl> Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Marc Bertens <mbertens@xs4all.nl> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5609 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Marc Bertens
committed by
Myles Watson
Myles Watson
parent
e3df121e4f
commit
2ad8ab8e7b
@ -23,3 +23,21 @@ config DRIVERS_SIL
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help
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help
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It sets PCI class to IDE compatible native mode, allowing
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It sets PCI class to IDE compatible native mode, allowing
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SeaBIOS, FILO etc... to boot from it.
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SeaBIOS, FILO etc... to boot from it.
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config DRIVERS_TI
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bool
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config DRIVERS_TI_PCI1225
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select DRIVERS_TI
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bool
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config DRIVERS_TI_PCI1420
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select DRIVERS_TI
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bool
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config DRIVERS_TI_PCI1520
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select DRIVERS_TI
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bool
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config DRIVERS_DEC_21143PD
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bool
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@ -1,3 +1,5 @@
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subdirs-y += generic/debug
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subdirs-y += generic/debug
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subdirs-y += ati/ragexl
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subdirs-y += ati/ragexl
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subdirs-y += sil/3114
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subdirs-y += sil/3114
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subdirs-y += ti/pcmcia-cardbus
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subdirs-y += dec/21143
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70
src/drivers/dec/21143/21143pd.c
Normal file
70
src/drivers/dec/21143/21143pd.c
Normal file
@ -0,0 +1,70 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <device/pci_def.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <console/console.h>
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/**
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* The following should be set in the mainboard-specific Kconfig file.
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*/
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#if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \
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!defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \
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!defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION))
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#error "you must supply these values in your mainboard-specific Kconfig file"
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#endif
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/* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */
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/* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */
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/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */
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/**
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* This driver take the values from Kconfig and load them in the registers
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*/
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static void dec_21143pd_enable( device_t dev )
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{
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printk( BIOS_DEBUG, "Init of DECchip 21143PD/TD Kconfig style\n");
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// Command and Status Configuration Register (Offset 0x04)
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pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION );
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printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) );
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// Cache Line Size Register (Offset 0x0C)
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pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE );
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printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) );
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// Expansion ROM Base Address Register (Offset 0x30)
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pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS );
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printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) );
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return;
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}
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static struct device_operations dec_21143pd_ops = {
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.read_resources = pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = dec_21143pd_enable,
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.scan_bus = 0,
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};
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static const struct pci_driver dec_21143pd_driver __pci_driver = {
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.ops = &dec_21143pd_ops,
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.vendor = PCI_VENDOR_ID_DEC,
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.device = PCI_DEVICE_ID_DEC_21142,
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};
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2
src/drivers/dec/21143/Makefile.inc
Normal file
2
src/drivers/dec/21143/Makefile.inc
Normal file
@ -0,0 +1,2 @@
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driver-$(CONFIG_DRIVERS_DEC_21143PD) += 21143pd.o
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2
src/drivers/ti/pcmcia-cardbus/Makefile.inc
Normal file
2
src/drivers/ti/pcmcia-cardbus/Makefile.inc
Normal file
@ -0,0 +1,2 @@
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driver-$(CONFIG_DRIVERS_TI) += ti-pcmcia-cardbus.o
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91
src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c
Normal file
91
src/drivers/ti/pcmcia-cardbus/ti-pcmcia-cardbus.c
Normal file
@ -0,0 +1,91 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#if ( !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \
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!defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) )
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#error "you must supply these values in your mainboard-specific Kconfig file"
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#endif
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static void ti_pci1x2y_init(struct device *dev)
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{
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printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
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// Command register (offset 04)
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pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR );
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// Cache Line Size Register (offset 0x0C)
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pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR );
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// CardBus latency timer register (offset 1B)
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pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR );
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// Bridge control register (offset 3E)
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pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR );
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/** Enable change sub-vendor id
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* Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */
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pci_write_config32( dev, 0x80, 0x10 );
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pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA );
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// Now write the correct value for SCR
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// System Control Register (offset 0x80)
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pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR );
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// Multifunction routing register
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pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR );
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// Set Device Control Register (0x92) accordingly
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pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 );
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return;
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}
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static struct device_operations ti_pci1x2y_ops = {
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.read_resources = NULL, //pci_dev_read_resources,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = ti_pci1x2y_init,
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.scan_bus = 0,
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};
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#ifdef CONFIG_DRIVERS_TI_PCI1225
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static const struct pci_driver ti_pci1225_driver __pci_driver = {
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.ops = &ti_pci1x2y_ops,
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.vendor = PCI_VENDOR_ID_TI,
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.device = PCI_DEVICE_ID_TI_1225,
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};
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#endif
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#ifdef CONFIG_DRIVERS_TI_PCI1420
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static const struct pci_driver ti_pci1420_driver __pci_driver = {
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.ops = &ti_pci1x2y_ops,
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.vendor = PCI_VENDOR_ID_TI,
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.device = PCI_DEVICE_ID_TI_1420,
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};
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#endif
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#ifdef CONFIG_DRIVERS_TI_PCI1520
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static const struct pci_driver ti_pci1520_driver __pci_driver = {
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.ops = &ti_pci1x2y_ops,
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.vendor = PCI_VENDOR_ID_TI,
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.device = PCI_DEVICE_ID_TI_1420,
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};
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#endif
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@ -696,6 +696,7 @@
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#define PCI_DEVICE_ID_TI_4410 0xac41
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#define PCI_DEVICE_ID_TI_4410 0xac41
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#define PCI_DEVICE_ID_TI_4451 0xac42
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#define PCI_DEVICE_ID_TI_4451 0xac42
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#define PCI_DEVICE_ID_TI_1420 0xac51
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#define PCI_DEVICE_ID_TI_1420 0xac51
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#define PCI_DEVICE_ID_TI_1520 0xAC55
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#define PCI_VENDOR_ID_SONY 0x104d
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#define PCI_VENDOR_ID_SONY 0x104d
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#define PCI_DEVICE_ID_SONY_CXD3222 0x8039
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#define PCI_DEVICE_ID_SONY_CXD3222 0x8039
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@ -1741,6 +1742,10 @@
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#define PCI_DEVICE_ID_CCD_B00C 0xb00c
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#define PCI_DEVICE_ID_CCD_B00C 0xb00c
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#define PCI_DEVICE_ID_CCD_B100 0xb100
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#define PCI_DEVICE_ID_CCD_B100 0xb100
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#define PCI_VENDOR_ID_NOKIA 0x13B8 // Nokia Telecommunications oy
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#define PCI_VENDOR_ID_NOKIA_WIRELESS 0x1603 // Nokia Wireless Communications
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#define PCI_VENDOR_ID_NOKIA_HOME 0x1622 // Nokia Home Communications
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#define PCI_VENDOR_ID_3WARE 0x13C1
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#define PCI_VENDOR_ID_3WARE 0x13C1
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#define PCI_DEVICE_ID_3WARE_1000 0x1000
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#define PCI_DEVICE_ID_3WARE_1000 0x1000
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@ -24,10 +24,12 @@ config BOARD_NOKIA_IP530
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select NORTHBRIDGE_INTEL_I440BX
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select NORTHBRIDGE_INTEL_I440BX
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select SOUTHBRIDGE_INTEL_I82371EB
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select SOUTHBRIDGE_INTEL_I82371EB
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select SUPERIO_SMSC_SMSCSUPERIO
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select SUPERIO_SMSC_SMSCSUPERIO
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select DRIVERS_TI_PCI1225
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select DRIVERS_DEC_21143PD
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select ROMCC
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select ROMCC
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select PIRQ_ROUTE
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select HAVE_PIRQ_TABLE
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select HAVE_PIRQ_TABLE
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select UDELAY_TSC
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select UDELAY_TSC
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select BOARD_ROMSIZE_KB_256
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config MAINBOARD_DIR
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config MAINBOARD_DIR
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string
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string
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@ -46,6 +48,52 @@ config HAVE_OPTION_TABLE
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config IRQ_SLOT_COUNT
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config IRQ_SLOT_COUNT
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int
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int
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default 6
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default 22
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depends on BOARD_NOKIA_IP530
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depends on BOARD_NOKIA_IP530
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## Configuration items for the ethernet adaptors
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config DEC21143_CACHE_LINE_SIZE
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int
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default 0x00000000
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depends on BOARD_NOKIA_IP530
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config DEC21143_EXPANSION_ROM_BASE_ADDRESS
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hex
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default 0x00000000
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depends on BOARD_NOKIA_IP530
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config DEC21143_COMMAND_AND_STATUS_CONFIGURATION
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hex
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default 0x02800107
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depends on BOARD_NOKIA_IP530
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## Configuration for the PCMCIA-Cardbus controller.
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config TI_PCMCIA_CARDBUS_CMDR
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hex
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default 0x0107
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depends on BOARD_NOKIA_IP530
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config TI_PCMCIA_CARDBUS_CLSR
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hex
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default 0x00
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depends on BOARD_NOKIA_IP530
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config TI_PCMCIA_CARDBUS_CLTR
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hex
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default 0x40
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depends on BOARD_NOKIA_IP530
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config TI_PCMCIA_CARDBUS_BCR
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hex
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default 0x07C0
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depends on BOARD_NOKIA_IP530
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config TI_PCMCIA_CARDBUS_SCR
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hex
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default 0x08449060
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depends on BOARD_NOKIA_IP530
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config TI_PCMCIA_CARDBUS_MRR
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hex
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default 0x00007522
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depends on BOARD_NOKIA_IP530
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@ -30,16 +30,8 @@ chip northbridge/intel/i440bx # Northbridge
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chip southbridge/intel/i82371eb # Southbridge
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chip southbridge/intel/i82371eb # Southbridge
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device pci 7.0 on # ISA bridge
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device pci 7.0 on # ISA bridge
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chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878)
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chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878)
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device pnp 3f0.0 on # Floppy
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device pnp 3f0.0 off end # Floppy (No connector)
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io 0x60 = 0x3f0
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device pnp 3f0.3 off end # Parallel port (No connector)
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 3f0.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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drq 0x74 = 4
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end
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device pnp 3f0.4 on # COM1
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device pnp 3f0.4 on # COM1
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io 0x60 = 0x3f8
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io 0x60 = 0x3f8
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irq 0x70 = 4
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irq 0x70 = 4
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@ -48,47 +40,23 @@ chip northbridge/intel/i440bx # Northbridge
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io 0x60 = 0x2f8
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io 0x60 = 0x2f8
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irq 0x70 = 3
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irq 0x70 = 3
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end
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end
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device pnp 3f0.7 on # PS/2 keyboard / mouse
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device pnp 3f0.7 on end # PS/2 keyboard / mouse
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io 0x60 = 0x60
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device pnp 3f0.6 on end # RTC
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io 0x62 = 0x64
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device pnp 3f0.8 on end # AUX I/O
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irq 0x70 = 1 # PS/2 keyboard interrupt
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device pnp 3f0.A off end # ACPI (No support yet)
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irq 0x72 = 12 # PS/2 mouse interrupt
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end
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device pnp 3f0.9 on # Game port
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io 0x60 = 0x201
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end
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device pnp 3f0.a on # Power-management events (PME)
|
|
||||||
io 0x60 = 0x600
|
|
||||||
end
|
|
||||||
device pnp 3f0.b on # MIDI port (MPU-401)
|
|
||||||
io 0x60 = 0x330
|
|
||||||
irq 0x70 = 5
|
|
||||||
end
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
device pci 7.1 on end # IDE
|
device pci 7.1 on end # IDE
|
||||||
device pci 7.2 on end # USB
|
device pci 7.2 off end # USB (No connector)
|
||||||
device pci 7.3 on end # ACPI
|
device pci 7.3 off end # ACPI (No support yet)
|
||||||
register "ide0_enable" = "1"
|
register "ide0_enable" = "1"
|
||||||
register "ide1_enable" = "1"
|
register "ide1_enable" = "1"
|
||||||
register "ide_legacy_enable" = "1"
|
register "ide_legacy_enable" = "1"
|
||||||
# Enable UDMA/33 for higher speed if your IDE device(s) support it.
|
# Disable UDMA/33 for lower speed if your IDE device(s) don't support it.
|
||||||
register "ide0_drive0_udma33_enable" = "0"
|
register "ide0_drive0_udma33_enable" = "1"
|
||||||
register "ide0_drive1_udma33_enable" = "0"
|
register "ide0_drive1_udma33_enable" = "1"
|
||||||
register "ide1_drive0_udma33_enable" = "0"
|
register "ide1_drive0_udma33_enable" = "1"
|
||||||
register "ide1_drive1_udma33_enable" = "0"
|
register "ide1_drive1_udma33_enable" = "1"
|
||||||
end
|
end
|
||||||
device pci 0d.0 on end # NIC (DEC DECchip 21142/43)
|
|
||||||
device pci 0e.0 on end # NIC (DEC DECchip 21142/43)
|
|
||||||
device pci 0f.0 on end # CardBus bridge (TI PCI1225)
|
|
||||||
device pci 0f.1 on end # CardBus bridge (TI PCI1225)
|
|
||||||
end
|
|
||||||
device pci_domain 1 on # PCI domain 1
|
|
||||||
device pci 00.0 on end # PCI bridge (DEC DECchip 21150)
|
|
||||||
end
|
|
||||||
device pci_domain 2 on # PCI domain 2
|
|
||||||
device pci 04.0 on end # NIC (DECchip 21142/43)
|
|
||||||
device pci 04.0 on end # NIC (DECchip 21142/43)
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|||||||
@ -31,15 +31,46 @@ const struct irq_routing_table intel_irq_routing_table = {
|
|||||||
0x122e, /* Device */
|
0x122e, /* Device */
|
||||||
0, /* Miniport */
|
0, /* Miniport */
|
||||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||||
0x36, /* Checksum */
|
0x44, /* Checksum */
|
||||||
{
|
{
|
||||||
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
/**
|
||||||
{0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
|
* Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
|
||||||
{0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
|
*/
|
||||||
{0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
|
// Southbridge 82371
|
||||||
{0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
|
{ 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
|
||||||
{0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
|
// On-board PCI-to-PCI bridge
|
||||||
{0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
|
{ 0x01, (0x00 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
|
||||||
|
// ETH1 on front panel
|
||||||
|
{ 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
|
||||||
|
// ETH2 on front panel
|
||||||
|
{ 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
|
||||||
|
// ETH3 on front panel
|
||||||
|
{ 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
|
||||||
|
// ETH4 on front panel
|
||||||
|
{ 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
|
||||||
|
// PCMCIA/Cardbus controller
|
||||||
|
{ 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
|
||||||
|
// Bridge for slot 1 (top)
|
||||||
|
{ 0x02, (0x07 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x64, 0x1E20}}, 0x0, 0x0 },
|
||||||
|
// PCI compact slots 1 (top)
|
||||||
|
{ 0x03, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x1, 0x0 },
|
||||||
|
{ 0x03, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x2, 0x0 },
|
||||||
|
{ 0x03, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x3, 0x0 },
|
||||||
|
{ 0x03, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x4, 0x0 },
|
||||||
|
// Bridge for slot 2 (middle)
|
||||||
|
{ 0x02, (0x06 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
|
||||||
|
// PCI compact slots 2 (middle)
|
||||||
|
{ 0x04, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x5, 0x0 },
|
||||||
|
{ 0x04, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x6, 0x0 },
|
||||||
|
{ 0x04, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x7, 0x0 },
|
||||||
|
{ 0x04, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x8, 0x0 },
|
||||||
|
// Bridge for slot 3 (bottom)
|
||||||
|
{ 0x00, (0x10 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
|
||||||
|
// PCI compact slots 3 (bottom)
|
||||||
|
{ 0x05, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x9, 0x0 },
|
||||||
|
{ 0x05, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0xA, 0x0 },
|
||||||
|
{ 0x05, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0xB, 0x0 },
|
||||||
|
{ 0x05, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0xC, 0x0 },
|
||||||
}
|
}
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -47,3 +78,13 @@ unsigned long write_pirq_routing_table(unsigned long addr)
|
|||||||
{
|
{
|
||||||
return copy_pirq_routing_table(addr);
|
return copy_pirq_routing_table(addr);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* TODO: This stub function is here until the point is solved in the
|
||||||
|
* main code of coreboot. see also arch/i386/boot/pirq_tables.c
|
||||||
|
*/
|
||||||
|
void pirq_assign_irqs(const unsigned char pIntAtoD[4])
|
||||||
|
{
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
|||||||
@ -20,7 +20,44 @@
|
|||||||
|
|
||||||
#include <device/device.h>
|
#include <device/device.h>
|
||||||
#include "chip.h"
|
#include "chip.h"
|
||||||
|
#include <device/pci_def.h>
|
||||||
|
#include <device/pci.h>
|
||||||
|
#include <arch/io.h>
|
||||||
|
#include <device/pnp_def.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
#define OUTB outb
|
||||||
|
#define INB inb
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Taken from flashrom project
|
||||||
|
* Generic Super I/O helper functions
|
||||||
|
*/
|
||||||
|
static uint8_t sio_read(uint16_t port, uint8_t reg)
|
||||||
|
{
|
||||||
|
OUTB( reg, port );
|
||||||
|
return ( INB( port + 1 ) );
|
||||||
|
}
|
||||||
|
|
||||||
|
static void sio_write(uint16_t port, uint8_t reg, uint8_t data)
|
||||||
|
{
|
||||||
|
OUTB( reg, port );
|
||||||
|
OUTB( data, port + 1 );
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void nokia_ip530_board_enable( device_t dev )
|
||||||
|
{
|
||||||
|
print_debug( "Setting up IP530-Super I/O devices\n");
|
||||||
|
sio_write( 0x20, 0x03, 0x80 );
|
||||||
|
printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) );
|
||||||
|
sio_write( 0x20, 0x22, 0x30 );
|
||||||
|
printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) );
|
||||||
|
sio_write( 0x20, 0x24, 0x84 );
|
||||||
|
printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) );
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
struct chip_operations mainboard_ops = {
|
struct chip_operations mainboard_ops = {
|
||||||
CHIP_NAME("Nokia IP530 Mainboard")
|
CHIP_NAME("Nokia IP530 Mainboard")
|
||||||
|
.enable_dev = nokia_ip530_board_enable,
|
||||||
};
|
};
|
||||||
|
|||||||
Reference in New Issue
Block a user