apollolake: update processor power limits configuration

Update processor power limit configuration parameters based on
common code base support for Intel Apollo Lake SoC based platforms.

BRANCH=None
BUG=None
TEST=Built and tested on octopus system

Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb

@@ -56,9 +56,11 @@ chip soc/intel/apollolake
 	register "dptf_enable" = "1"
 
 	# PL1 override: 7.5W setting gives a run-time 6W actual
-	register "tdp_pl1_override_mw" = "7500"
 	# Set RAPL PL2 to 15W.
-	register "tdp_pl2_override_mw" = "15000"
+	register "power_limits_config" = "{
+		.tdp_pl1_override = 7,
+		.tdp_pl2_override = 15,
+	}"
 
 	# Enable Audio Clock and Power gating
 	register "hdaudio_clk_gate_enable" = "1"