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coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3

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a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2009-02-28 20:10:20 +00:00
committed by Stefan Reinauer
parent 3c924d2f48
commit 2b34db8d1d
99 changed files with 433 additions and 345 deletions
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14
src/mainboard/amd/dbm690t/mainboard.c
View File

@@ -105,24 +105,24 @@ static void get_ide_dma66()
byte =
pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0xA9);
sm_dev->path.pci.devfn, 0xA9);
byte |= (1 << 5); /* Set Gpio9 as input */
pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0xA9, byte);
sm_dev->path.pci.devfn, 0xA9, byte);
ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
byte =
pci_cf8_conf1.read8(&pbus, ide_dev->bus->secondary,
ide_dev->path.u.pci.devfn, 0x56);
ide_dev->path.pci.devfn, 0x56);
byte &= ~(7 << 0);
if ((1 << 5) & pci_cf8_conf1.
read8(&pbus, sm_dev->bus->secondary, sm_dev->path.u.pci.devfn,
read8(&pbus, sm_dev->bus->secondary, sm_dev->path.pci.devfn,
0xAA))
byte |= 2 << 0; /* mode 2 */
else
byte |= 5 << 0; /* mode 5 */
pci_cf8_conf1.write8(&pbus, ide_dev->bus->secondary,
ide_dev->path.u.pci.devfn, 0x56, byte);
ide_dev->path.pci.devfn, 0x56, byte);
}
/*
@@ -158,10 +158,10 @@ static void set_thermal_config()
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
word =
pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x56);
sm_dev->path.pci.devfn, 0x56);
word |= 1 << 7;
pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x56, word);
sm_dev->path.pci.devfn, 0x56, word);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);

16
src/mainboard/amd/pistachio/mainboard.c
View File

@@ -169,26 +169,26 @@ static void set_thermal_config()
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
dword =
pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x64);
sm_dev->path.pci.devfn, 0x64);
dword |= 1 << 19;
pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x64, dword);
sm_dev->path.pci.devfn, 0x64, dword);
/* Enable Client Management Index/Data registers */
dword =
pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x78);
sm_dev->path.pci.devfn, 0x78);
dword |= 1 << 11; /* Cms_enable */
pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x78, dword);
sm_dev->path.pci.devfn, 0x78, dword);
/* MiscfuncEnable */
byte =
pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x41);
sm_dev->path.pci.devfn, 0x41);
byte |= (1 << 5);
pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x41, byte);
sm_dev->path.pci.devfn, 0x41, byte);
/* set GPM5 as input */
/* set index register 0C50h to 13h (miscellaneous control) */
@@ -230,10 +230,10 @@ static void set_thermal_config()
/* set GPIO 64 to input */
word =
pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x56);
sm_dev->path.pci.devfn, 0x56);
word |= 1 << 7;
pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary,
sm_dev->path.u.pci.devfn, 0x56, word);
sm_dev->path.pci.devfn, 0x56, word);
/* set GPIO 64 internal pull-up */
byte = pm2_ioread(0xf0);