tests: Add lib/spd_cache-test test case
Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Change-Id: Ic9a1420e49e1e80d180117c931e630e54c90cd75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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committed by
Patrick Georgi
parent
bfa60433cb
commit
2b8d7216ef
@@ -28,6 +28,8 @@ tests-y += bootmem-test
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tests-y += dimm_info_util-test
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tests-y += coreboot_table-test
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tests-y += rtc-test
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tests-y += spd_cache-ddr3-test
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tests-y += spd_cache-ddr4-test
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string-test-srcs += tests/lib/string-test.c
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string-test-srcs += src/lib/string.c
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@@ -144,3 +146,24 @@ coreboot_table-test-mocks += cbmem_top_chipset
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rtc-test-srcs += tests/lib/rtc-test.c
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rtc-test-srcs += src/lib/rtc.c
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spd_cache-ddr3-test-srcs += tests/lib/spd_cache-test.c
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spd_cache-ddr3-test-srcs += tests/stubs/console.c
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spd_cache-ddr3-test-srcs += src/lib/spd_cache.c
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spd_cache-ddr3-test-srcs += src/lib/crc_byte.c
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spd_cache-ddr3-test-srcs += src/commonlib/region.c
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spd_cache-ddr3-test-mocks += fmap_locate_area_as_rdev
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spd_cache-ddr3-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"RW_SPD_CACHE\" \
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CONFIG_DIMM_MAX=4 CONFIG_DIMM_SPD_SIZE=256 \
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CONFIG_BOOT_DEVICE_MEMORY_MAPPED=1
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spd_cache-ddr3-test-cflags += -D__TEST_SPD_CACHE_DDR=3
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spd_cache-ddr4-test-srcs += tests/lib/spd_cache-test.c
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spd_cache-ddr4-test-srcs += tests/stubs/console.c
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spd_cache-ddr4-test-srcs += src/lib/spd_cache.c
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spd_cache-ddr4-test-srcs += src/lib/crc_byte.c
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spd_cache-ddr4-test-srcs += src/commonlib/region.c
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spd_cache-ddr4-test-mocks += fmap_locate_area_as_rdev
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spd_cache-ddr4-test-config += CONFIG_SPD_CACHE_FMAP_NAME=\"RW_SPD_CACHE\" \
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CONFIG_DIMM_MAX=4 CONFIG_DIMM_SPD_SIZE=512 \
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CONFIG_BOOT_DEVICE_MEMORY_MAPPED=1
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spd_cache-ddr4-test-cflags += -D__TEST_SPD_CACHE_DDR=4
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