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uart8250mem: Unify calls with generic UART

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NOTE: UART base for SMM continues to be broken, as it does not use
the address resource allocator has assigned.

Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kyösti Mälkki
2014-02-15 10:19:23 +02:00
parent 4770749edc
commit 2b95da01e6
10 changed files with 104 additions and 126 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/drivers/oxford/oxpcie/Makefile.inc
View File

@@ -1,5 +1,4 @@
ramstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c
ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y)
romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c
ramstage-y += oxpcie_early.c oxpcie.c
romstage-y += oxpcie_early.c
endif

7
src/drivers/oxford/oxpcie/oxpcie.c
View File

@@ -22,7 +22,7 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <console/console.h>
#include <uart8250.h>
#include <console/uart.h>
#include <arch/io.h>
static void oxford_oxpcie_enable(device_t dev)
@@ -47,10 +47,9 @@ static void oxford_oxpcie_set_resources(struct device *dev)
{
pci_dev_set_resources(dev);
#if CONFIG_CONSOLE_SERIAL8250MEM
/* Re-initialize OXPCIe base address after set_resources */
uartmem_init();
#endif
u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
oxford_remap(mmio_base & ~0xf);
}
static struct device_operations oxford_oxpcie_ops = {

52
src/drivers/oxford/oxpcie/oxpcie_early.c
View File

@@ -17,14 +17,20 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#define __SIMPLE_DEVICE__
#include <stdint.h>
#include <stddef.h>
#include <arch/io.h>
#include <arch/early_variables.h>
#include <delay.h>
#include <console/uart.h>
#include <uart8250.h>
#include <device/pci_def.h>
static unsigned int oxpcie_present CAR_GLOBAL;
static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000;
#define PCIE_BRIDGE \
PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \
CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \
@@ -36,13 +42,9 @@
#define OXPCIE_DEVICE_3 \
PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
#if defined(__PRE_RAM__)
int oxford_oxpcie_present CAR_GLOBAL;
void oxford_init(void)
static void oxpcie_init_bridge(void)
{
u16 reg16;
oxford_oxpcie_present = 1;
/* First we reset the secondary bus */
reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
@@ -101,7 +103,6 @@ void oxford_init(void)
break;
default:
/* No UART here. */
oxford_oxpcie_present = 0;
return;
}
@@ -114,17 +115,42 @@ void oxford_init(void)
reg16 |= PCI_COMMAND_MEMORY;
pci_write_config16(device, PCI_COMMAND, reg16);
/* Now the UART initialization */
u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
unsigned int div = uart_baudrate_divisor(default_baudrate(),
uart_platform_refclk(), 16);
uart8250_mem_init(uart0_base, div);
car_set_var(oxpcie_present, 1);
}
static int oxpcie_uart_active(void)
{
return (car_get_var(oxpcie_present));
}
unsigned int uart_platform_base(int idx)
{
if (idx == 0 && oxpcie_uart_active())
return uart0_base;
if (idx == 1 && oxpcie_uart_active())
return uart1_base;
return 0;
}
#ifndef __PRE_RAM__
void oxford_remap(u32 new_base)
{
uart0_base = new_base + 0x1000;
uart1_base = new_base + 0x2000;
}
uint32_t uartmem_getbaseaddr(void)
{
return uart_platform_base(0);
}
#endif
unsigned int uart_platform_refclk(void)
{
return 62500000;
}
void oxford_init(void)
{
oxpcie_init_bridge();
}