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soc/intel/apollolake: Fix northbridge _crs scope

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Move _CRS scope from MCHC device only to whole pci root bus. Otherwise
ACPI will not able to assign resource to devices other than MCHC.

Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3
Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/14477
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Zhao, Lijian 2016-04-22 11:19:44 -07:00 committed by Aaron Durbin
parent cbf1a0fec8
commit 2b9a5f5688
1 changed files with 94 additions and 93 deletions
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25
src/soc/intel/apollolake/acpi/northbridge.asl
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@ -36,8 +36,9 @@ Device (MCHC)
Offset(0xBC), Offset(0xBC),
TLUD, 32, /* Top of Low Useable DRAM */ TLUD, 32, /* Top of Low Useable DRAM */
} }
Name (MCRS, ResourceTemplate() }
{ Name (MCRS, ResourceTemplate()
{
/* Bus Numbers */ /* Bus Numbers */
WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,)
@ -81,11 +82,11 @@ Device (MCHC)
NonCacheable, ReadWrite, NonCacheable, ReadWrite,
0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x00000000, 0x10000, 0x1ffff, 0x00000000,
0x10000,,, PM02) 0x10000,,, PM02)
}) })
/* Current Resource Settings */ /* Current Resource Settings */
Method (_CRS, 0, Serialized) Method (_CRS, 0, Serialized)
{ {
/* Find PCI resource area in MCRS */ /* Find PCI resource area in MCRS */
CreateDwordField (MCRS, ^PM01._MIN, PMIN) CreateDwordField (MCRS, ^PM01._MIN, PMIN)
@ -93,9 +94,9 @@ Device (MCHC)
CreateDwordField (MCRS, ^PM01._LEN, PLEN) CreateDwordField (MCRS, ^PM01._LEN, PLEN)
/* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */
And(^TLUD, 0xFFF00000, PMIN) And(^MCHC.TLUD, 0xFFF00000, PMIN)
/* Read MMCONF base */ /* Read MMCONF base */
And(^MCNF, 0xF0000000, PMAX) And(^MCHC.MCNF, 0xF0000000, PMAX)
/* Calculate PCI MMIO Length */ /* Calculate PCI MMIO Length */
Add(Subtract(PMAX, PMIN), 1, PLEN) Add(Subtract(PMAX, PMIN), 1, PLEN)
@ -106,10 +107,10 @@ Device (MCHC)
CreateDwordField(MCRS, ^STOM._LEN, GLEN) CreateDwordField(MCRS, ^STOM._LEN, GLEN)
/* Read BGSM */ /* Read BGSM */
And(^BGSM, 0xFFF00000, GMIN) And(^MCHC.BGSM, 0xFFF00000, GMIN)
/* Read TOLUD */ /* Read TOLUD */
And(^TLUD, 0xFFF00000, GMAX) And(^MCHC.TLUD, 0xFFF00000, GMAX)
Decrement(GMAX) Decrement(GMAX)
Add(Subtract(GMAX, GMIN), 1, GLEN) Add(Subtract(GMAX, GMIN), 1, GLEN)
@ -118,7 +119,7 @@ Device (MCHC)
CreateQwordField (MCRS, ^PM02._MAX, MMAX) CreateQwordField (MCRS, ^PM02._MAX, MMAX)
CreateQwordField (MCRS, ^PM02._LEN, MLEN) CreateQwordField (MCRS, ^PM02._LEN, MLEN)
Store (^TUUD, Local0) Store (^MCHC.TUUD, Local0)
If (LLessEqual (Local0, 0x1000000000)) If (LLessEqual (Local0, 0x1000000000))
{ {
@ -128,5 +129,5 @@ Device (MCHC)
Subtract (Add (MMIN, MLEN), 1, MMAX) Subtract (Add (MMIN, MLEN), 1, MMAX)
Return (MCRS) Return (MCRS)
}
} }