cpu/nb/sb: Remove fam12

With removal of Torpedo mainboard, this code is no longer necessary. This also removes fam12 support from northbridge and SB900 from southbridge. Change-Id: I8a30461278844d0d9ad4320f0e952774c4fd644f Signed-off-by: Joe Moore <awokd@danwin1210.me> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-10-21 01:03:08 -06:00
parent dc0b1875a9
commit 2c08ea7cfc
37 changed files with 0 additions and 4164 deletions
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -13,7 +13,6 @@

 config CPU_AMD_AGESA
 	bool
-	default y if CPU_AMD_AGESA_FAMILY12
 	default y if CPU_AMD_AGESA_FAMILY14
 	default y if CPU_AMD_AGESA_FAMILY15_TN
 	default y if CPU_AMD_AGESA_FAMILY16_KB
@@ -67,7 +66,6 @@ config S3_DATA_SIZE

 endif # CPU_AMD_AGESA

-source src/cpu/amd/agesa/family12/Kconfig
 source src/cpu/amd/agesa/family14/Kconfig
 source src/cpu/amd/agesa/family15tn/Kconfig
 source src/cpu/amd/agesa/family16kb/Kconfig
--- a/src/cpu/amd/agesa/Makefile.inc
+++ b/src/cpu/amd/agesa/Makefile.inc
@@ -10,7 +10,6 @@
 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 # GNU General Public License for more details.
 #
-subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY12) += family12
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY14) += family14
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb
--- a/src/cpu/amd/agesa/family12/Kconfig
+++ b/src/cpu/amd/agesa/family12/Kconfig
@@ -1,24 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-config CPU_AMD_AGESA_FAMILY12
-	bool
-	select X86_AMD_FIXED_MTRRS
-
-if CPU_AMD_AGESA_FAMILY12
-
-config CPU_ADDR_BITS
-	int
-	default 48
-
-endif
--- a/src/cpu/amd/agesa/family12/Makefile.inc
+++ b/src/cpu/amd/agesa/family12/Makefile.inc
@@ -1,43 +0,0 @@
-#*****************************************************************************
-#
-# Copyright (c) 2011, Advanced Micro Devices, Inc.
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are met:
-#     * Redistributions of source code must retain the above copyright
-#       notice, this list of conditions and the following disclaimer.
-#     * Redistributions in binary form must reproduce the above copyright
-#       notice, this list of conditions and the following disclaimer in the
-#       documentation and/or other materials provided with the distribution.
-#     * Neither the name of Advanced Micro Devices, Inc. nor the names of
-#       its contributors may be used to endorse or promote products derived
-#       from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
-# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-#*****************************************************************************
-
-romstage-y += fixme.c
-romstage-y += romstage.c
-
-ramstage-y += fixme.c
-ramstage-y += chip_name.c
-ramstage-y += model_12_init.c
-
-subdirs-y += ../../mtrr
-subdirs-y += ../../../x86/tsc
-subdirs-y += ../../../x86/lapic
-subdirs-y += ../../../x86/cache
-subdirs-y += ../../../x86/mtrr
-subdirs-y += ../../../x86/pae
-subdirs-y += ../../../x86/smm
--- a/src/cpu/amd/agesa/family12/chip_name.c
+++ b/src/cpu/amd/agesa/family12/chip_name.c
@@ -1,18 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-struct chip_operations cpu_amd_agesa_family12_ops = {
-	CHIP_NAME("AMD CPU Family 12h")
-};
--- a/src/cpu/amd/agesa/family12/fixme.c
+++ b/src/cpu/amd/agesa/family12/fixme.c
@@ -1,103 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-#include <AGESA.h>
-#include <amdlib.h>
-
-void amd_initcpuio(void)
-{
-	UINT64 MsrReg;
-	UINT32 PciData;
-	PCI_ADDR PciAddress;
-	AMD_CONFIG_PARAMS StdHeader;
-
-	/* Enable MMIO on AMD CPU Address Map Controller */
-
-	/* Start to set MMIO 0000A0000-0000BFFFF to Node0 Link0 */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
-	PciData = 0x00000B00;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
-	PciData = 0x00000A03;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Set TOM-DFFFFFFF to Node0 Link0. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
-	PciData = 0x00DFFF00;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
-	MsrReg = (MsrReg >> 8) | 3;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
-	PciData = (UINT32) MsrReg;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Set E0000000-FFFFFFFF to Node0 Link0 with NP set. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xBC);
-	PciData = 0x00FFFF00 | 0x80;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xB8);
-	PciData = (CONFIG_MMCONF_BASE_ADDRESS >> 8) | 03;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Start to set PCIIO 0000-FFFF to Node0 Link0 with ISA&VGA set. */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
-//-  PciData = 0x0000F000;
-	PciData = 0x00FFF000;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
-	PciData = 0x00000013;
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-}
-
-void amd_initmmio(void)
-{
-	UINT64 MsrReg;
-	UINT32 PciData;
-	PCI_ADDR PciAddress;
-	AMD_CONFIG_PARAMS StdHeader;
-
-	/*
-	   Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base
-	   Address MSR register.
-	 */
-	MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1;
-	LibAmdMsrWrite(MMIO_CONF_BASE, &MsrReg, &StdHeader);
-
-	/* Enable Non-Post Memory in CPU */
-	PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;
-	PciData = (PciData >> 8) & ~0xff;
-	PciData |= 0x80;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA4);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	PciData = ((CONFIG_MMCONF_BASE_ADDRESS >> 8) | 0x03);
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x018, 0x01, 0xA0);
-	LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
-
-	/* Enable memory access */
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
-	LibAmdPciRead(AccessWidth8, PciAddress, &PciData, &StdHeader);
-	PciData |= BIT1;
-	PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0, 0, 0x04);
-	LibAmdPciWrite(AccessWidth8, PciAddress, &PciData, &StdHeader);
-
-	/* Set ROM cache onto WP to decrease post time */
-	MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull;
-	LibAmdMsrWrite(MTRR_PHYS_BASE(6), &MsrReg, &StdHeader);
-	MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
-	LibAmdMsrWrite(MTRR_PHYS_MASK(6), &MsrReg, &StdHeader);
-}
--- a/src/cpu/amd/agesa/family12/model_12_init.c
+++ b/src/cpu/amd/agesa/family12/model_12_init.c
@@ -1,106 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/msr.h>
-#include <cpu/x86/mtrr.h>
-#include <cpu/amd/mtrr.h>
-#include <device/device.h>
-#include <cpu/x86/pae.h>
-#include <cpu/x86/lapic.h>
-#include <cpu/cpu.h>
-#include <cpu/x86/cache.h>
-#include <cpu/amd/multicore.h>
-
-static void model_12_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "Model 12 Init.\n");
-
-	u8 i;
-	msr_t msr;
-	int num_banks;
-
-#if CONFIG(LOGICAL_CPUS)
-	u32 siblings;
-#endif
-
-//  struct node_core_id id;
-//  id = get_node_core_id(read_nb_cfg_54());  /* nb_cfg_54 can not be set */
-//  printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
-
-	/* Turn on caching if we haven't already */
-	x86_enable_cache();
-	amd_setup_mtrrs();
-	x86_mtrr_check();
-
-	disable_cache();
-
-	/* zero the machine check error status registers */
-	msr = rdmsr(IA32_MCG_CAP);
-	num_banks = msr.lo & MCA_BANKS_MASK;
-	msr.lo = 0;
-	msr.hi = 0;
-	for (i = 0; i < num_banks; i++)
-		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
-
-	enable_cache();
-
-	/* Enable the local CPU APICs */
-	setup_lapic();
-
-	/* Set the processor name string */
-	//  init_processor_name();
-
-#if CONFIG(LOGICAL_CPUS)
-	siblings = cpuid_ecx(0x80000008) & 0xff;
-
-	if (siblings > 0) {
-		msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
-		msr.lo |= 1 << 28;
-		wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
-
-		msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
-		msr.hi |= 1 << (33 - 32);
-		wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
-	}
-	printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
-#endif
-
-	/* DisableCf8ExtCfg */
-	msr = rdmsr(NB_CFG_MSR);
-	msr.hi &= ~(1 << (46 - 32));
-	wrmsr(NB_CFG_MSR, msr);
-
-	/* Write protect SMM space with SMMLOCK. */
-	msr = rdmsr(HWCR_MSR);
-	msr.lo |= (1 << 0);
-	wrmsr(HWCR_MSR, msr);
-}
-
-static struct device_operations cpu_dev_ops = {
-	.init = model_12_init,
-};
-
-static const struct cpu_device_id cpu_table[] = {
-	{ X86_VENDOR_AMD, 0x300f00 },   /* LN1_A0x */
-	{ X86_VENDOR_AMD, 0x300f01 },   /* LN1_A1x */
-	{ X86_VENDOR_AMD, 0x300f10 },   /* LN1_B0x */
-	{ X86_VENDOR_AMD, 0x300f20 },   /* LN2_B0x */
-	{ 0, 0 },
-};
-
-static const struct cpu_driver model_12 __cpu_driver = {
-	.ops      = &cpu_dev_ops,
-	.id_table = cpu_table,
-};
--- a/src/cpu/amd/agesa/family12/romstage.c
+++ b/src/cpu/amd/agesa/family12/romstage.c
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <northbridge/amd/agesa/state_machine.h>
-
-#include "sb_cimx.h"
-#include "SbPlatform.h"
-#include "platform_cfg.h"
-
-void platform_once(struct sysinfo *cb)
-{
-	gpioEarlyInit();
-
-	sb_poweron_init();
-
-	board_BeforeAgesa(cb);
-}
--- a/src/northbridge/amd/agesa/Makefile.inc
+++ b/src/northbridge/amd/agesa/Makefile.inc
@@ -15,7 +15,6 @@

 ifeq ($(CONFIG_NORTHBRIDGE_AMD_AGESA),y)

-subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) += family12
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) += family14
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb
--- a/src/northbridge/amd/agesa/family12/Kconfig
+++ b/src/northbridge/amd/agesa/family12/Kconfig
@@ -1,35 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-config NORTHBRIDGE_AMD_AGESA_FAMILY12
-	bool
-	select HAVE_DEBUG_RAM_SETUP
-	select HAVE_DEBUG_SMBUS
-	select HYPERTRANSPORT_PLUGIN_SUPPORT
-
-if NORTHBRIDGE_AMD_AGESA_FAMILY12
-
-config HW_MEM_HOLE_SIZEK
-	hex
-	default 0x100000
-
-config MMCONF_BASE_ADDRESS
-	hex
-	default 0xe0000000
-
-config MMCONF_BUS_NUMBER
-	int
-	default 256
-
-endif # NORTHBRIDGE_AMD_AGESA_FAMILY_12
--- a/src/northbridge/amd/agesa/family12/Makefile.inc
+++ b/src/northbridge/amd/agesa/family12/Makefile.inc
@@ -1,21 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-romstage-y += dimmSpd.c
-
-ramstage-y += northbridge.c
-
-romstage-y += state_machine.c
-ramstage-y += state_machine.c
--- a/src/northbridge/amd/agesa/family12/dimmSpd.c
+++ b/src/northbridge/amd/agesa/family12/dimmSpd.c
@@ -1,80 +0,0 @@
-/*
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-
-#include <stdlib.h>
-#include <Porting.h>
-#include <AGESA.h>
-
-#include <northbridge/amd/agesa/dimmSpd.h>
-
-typedef struct _DIMM_INFO_SMBUS {
-	UINT8   SocketId;
-	UINT8   MemChannelId;
-	UINT8   DimmId;
-	UINT8   SmbusAddress;
-} DIMM_INFO_SMBUS;
-
-/*
-* SPD address table - porting required
-*/
-STATIC CONST DIMM_INFO_SMBUS SpdAddrLookup [] =
-{
-	/* Socket, Channel, Dimm, Smbus */
-	{0, 0, 0, 0xA0},
-	{0, 1, 0, 0xA2}
-};
-
-AGESA_STATUS
-AmdMemoryReadSPD (
-  IN UINT32 Func,
-  IN UINTN Data,
-  IN OUT AGESA_READ_SPD_PARAMS *SpdData
- )
-{
-	UINT8  SmBusAddress = 0;
-	UINTN  Index;
-	UINTN  MaxSocket = ARRAY_SIZE(SpdAddrLookup);
-
-	for (Index = 0; Index < MaxSocket; Index ++) {
-		if ((SpdData->SocketId     == SpdAddrLookup[Index].SocketId)     &&
-				(SpdData->MemChannelId == SpdAddrLookup[Index].MemChannelId) &&
-				(SpdData->DimmId       == SpdAddrLookup[Index].DimmId)) {
-			SmBusAddress = SpdAddrLookup[Index].SmbusAddress;
-			break;
-		}
-	}
-
-	if (SmBusAddress == 0)
-		return AGESA_ERROR;
-
-	int err = smbus_readSpd(SmBusAddress, (char *) SpdData->Buffer, 128);
-	if (err)
-		return AGESA_ERROR;
-	return AGESA_SUCCESS;
-}
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -1,834 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <arch/acpi.h>
-#include <arch/acpigen.h>
-#include <device/pci_ops.h>
-#include <stdint.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/hypertransport.h>
-#include <stdlib.h>
-#include <string.h>
-#include <lib.h>
-#include <cpu/cpu.h>
-
-#include <cpu/x86/lapic.h>
-#include <cpu/amd/msr.h>
-#include <cpu/amd/mtrr.h>
-
-#include "sb_cimx.h"
-
-#include <northbridge/amd/agesa/nb_common.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-#define FX_DEVS 1
-
-static struct device *__f0_dev[FX_DEVS];
-static struct device *__f1_dev[FX_DEVS];
-static struct device *__f2_dev[FX_DEVS];
-static struct device *__f4_dev[FX_DEVS];
-static unsigned int fx_devs = 0;
-
-struct dram_base_mask_t {
-	u32 base; //[47:27] at [28:8]
-	u32 mask; //[47:27] at [28:8] and enable at bit 0
-};
-
-static struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
-{
-	struct device *dev;
-	struct dram_base_mask_t d;
-	dev = __f1_dev[0];
-
-	u32 temp;
-	temp = pci_read_config32(dev, 0x44); //[39:24] at [31:16]
-	d.mask = (temp & 0xffff0000); // mask out  DramMask [26:24] too
-
-	temp = pci_read_config32(dev, 0x40); //[35:24] at [27:16]
-	d.mask |= (temp & 1); // read enable bit
-
-	d.base = (temp & 0x0fff0000); // mask out DramBase [26:24) too
-
-	return d;
-}
-
-static u32 get_io_addr_index(u32 nodeid, u32 linkn)
-{
-	return 0;
-}
-
-static u32 get_mmio_addr_index(u32 nodeid, u32 linkn)
-{
-	return 0;
-}
-
-static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
-			    u32 io_min, u32 io_max)
-{
-
-	u32 tempreg;
-	/* io range allocation */
-	tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) |
-		  ((io_max & 0xf0) << (12 - 4)); //limit
-	pci_write_config32(__f1_dev[0], reg+4, tempreg);
-
-	tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ?
-	pci_write_config32(__f1_dev[0], reg, tempreg);
-}
-
-static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index,
-			      u32 mmio_min, u32 mmio_max, u32 nodes)
-{
-
-	u32 tempreg;
-	/* io range allocation */
-	tempreg = (nodeid & 0xf) | (linkn << 4) | (mmio_max & 0xffffff00);
-	pci_write_config32(__f1_dev[0], reg+4, tempreg);
-	tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00);
-	pci_write_config32(__f1_dev[0], reg, tempreg);
-}
-
-static struct device *get_node_pci(u32 nodeid, u32 fn)
-{
-	return pcidev_on_root(DEV_CDB + nodeid, fn);
-}
-
-static void get_fx_devs(void)
-{
-	int i;
-	for (i = 0; i < FX_DEVS; i++) {
-		__f0_dev[i] = get_node_pci(i, 0);
-		__f1_dev[i] = get_node_pci(i, 1);
-		__f2_dev[i] = get_node_pci(i, 2);
-		__f4_dev[i] = get_node_pci(i, 4);
-		if (__f0_dev[i] != NULL && __f1_dev[i] != NULL)
-			fx_devs = i+1;
-	}
-
-	if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0)
-		die("Cannot find 0:0x18.[0|1]\n");
-}
-
-static u32 f1_read_config32(unsigned int reg)
-{
-	if (fx_devs == 0)
-		get_fx_devs();
-
-	return pci_read_config32(__f1_dev[0], reg);
-}
-
-static void f1_write_config32(unsigned int reg, u32 value)
-{
-	int i;
-	if (fx_devs == 0)
-		get_fx_devs();
-	for (i = 0; i < fx_devs; i++) {
-		struct device *dev = __f1_dev[i];
-		if (dev && dev->enabled) {
-			pci_write_config32(dev, reg, value);
-		}
-	}
-}
-
-static u32 amdfam12_nodeid(struct device *dev)
-{
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__);
-	return (dev->path.pci.devfn >> 3) - DEV_CDB;
-}
-
-static void northbridge_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "Northbridge init\n");
-}
-
-
-static void set_vga_enable_reg(u32 nodeid, u32 linkn)
-{
-	u32 val;
-
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-	val =  1 | (nodeid << 4) | (linkn << 12);
-	/* it will routing (1)mmio  0xa0000:0xbffff (2) io 0x3b0:0x3bb,
-	   0x3c0:0x3df */
-	f1_write_config32(0xf4, val);
-
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-
-static int reg_useable(unsigned int reg, struct device *goal_dev,
-		       unsigned int goal_nodeid, unsigned int goal_link)
-{
-	struct resource *res;
-	unsigned int nodeid, link = 0;
-	int result;
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-	res = 0;
-	for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) {
-		struct device *dev = __f0_dev[nodeid];
-		if (!dev)
-			continue;
-		for (link = 0; !res && (link < 8); link++) {
-			res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
-		}
-	}
-	result = 2;
-	if (res) {
-		result = 0;
-		if ((goal_link == (link - 1)) &&
-		    (goal_nodeid == (nodeid - 1)) &&
-		    (res->flags <= 1)) {
-			result = 1;
-		}
-	}
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-	return result;
-}
-
-static struct resource *amdfam12_find_iopair(struct device *dev,
-					unsigned int nodeid, unsigned int link)
-{
-	struct resource *resource;
-	u32 result, reg;
-	resource = 0;
-	reg = 0;
-	result = reg_useable(0xc0, dev, nodeid, link);
-	if (result >= 1) {
-		/* I have been allocated this one */
-		reg = 0xc0;
-	}
-
-	//Ext conf space
-	if (!reg) {
-		//because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range
-		u32 index = get_io_addr_index(nodeid, link);
-		reg = 0x110+ (index << 24) + (4 << 20); // index could be 0, 255
-	}
-
-	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
-
-	return resource;
-}
-
-static struct resource *amdfam12_find_mempair(struct device *dev, u32 nodeid,
-					      u32 link)
-{
-	struct resource *resource;
-	u32 free_reg, reg;
-	resource = 0;
-	free_reg = 0;
-	for (reg = 0x80; reg <= 0xb8; reg += 0x8) {
-		int result;
-		result = reg_useable(reg, dev, nodeid, link);
-		if (result == 1) {
-			/* I have been allocated this one */
-			break;
-		}
-		else if (result > 1) {
-			/* I have a free register pair */
-			free_reg = reg;
-		}
-	}
-	if (reg > 0xb8) {
-		reg = free_reg;
-	}
-
-	//Ext conf space
-	if (!reg) {
-		//because of Extend conf space, we will never run out of reg,
-		// but we need one index to differ them. so same node and
-		// same link can have multi range
-		u32 index = get_mmio_addr_index(nodeid, link);
-		reg = 0x110+ (index << 24) + (6 << 20); // index could be 0, 63
-	}
-
-	resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
-	return resource;
-}
-
-
-static void amdfam12_link_read_bases(struct device *dev, u32 nodeid, u32 link)
-{
-	struct resource *resource;
-
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-	/* Initialize the io space constraints on the current bus */
-	resource = amdfam12_find_iopair(dev, nodeid, link);
-	if (resource) {
-		u32 align;
-		align = log2(HT_IO_HOST_ALIGN);
-		resource->base  = 0;
-		resource->size  = 0;
-		resource->align = align;
-		resource->gran  = align;
-		resource->limit = 0xffffUL;
-		resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
-	}
-
-	/* Initialize the prefetchable memory constraints on the current bus */
-	resource = amdfam12_find_mempair(dev, nodeid, link);
-	if (resource) {
-		resource->base = 0;
-		resource->size = 0;
-		resource->align = log2(HT_MEM_HOST_ALIGN);
-		resource->gran = log2(HT_MEM_HOST_ALIGN);
-		resource->limit = 0xffffffffffULL;
-		resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
-		resource->flags |= IORESOURCE_BRIDGE;
-	}
-
-	/* Initialize the memory constraints on the current bus */
-	resource = amdfam12_find_mempair(dev, nodeid, link);
-	if (resource) {
-		resource->base = 0;
-		resource->size = 0;
-		resource->align = log2(HT_MEM_HOST_ALIGN);
-		resource->gran = log2(HT_MEM_HOST_ALIGN);
-		resource->limit = 0xffffffffffULL;
-		resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
-	}
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
-{
-	struct resource *min;
-	min = 0;
-	search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
-	if (min && tolm > min->base) {
-		tolm = min->base;
-	}
-	return tolm;
-}
-
-#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-
-struct hw_mem_hole_info {
-	unsigned int hole_startk;
-	int node_id;
-};
-
-static struct hw_mem_hole_info get_hw_mem_hole_info(void)
-{
-	struct hw_mem_hole_info mem_hole;
-
-	mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
-	mem_hole.node_id = -1;
-
-	struct dram_base_mask_t d;
-	u32 hole;
-	d = get_dram_base_mask(0);
-	if (d.mask & 1) {
-		hole = pci_read_config32(__f1_dev[0], 0xf0);
-		if (hole & 1) { // we find the hole
-			mem_hole.hole_startk = (hole & (0xff << 24)) >> 10;
-			mem_hole.node_id = 0; // record the node No with hole
-		}
-	}
-	return mem_hole;
-}
-#endif
-
-static void read_resources(struct device *dev)
-{
-	u32 nodeid;
-	struct bus *link;
-
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
-	nodeid = amdfam12_nodeid(dev);
-	for (link = dev->link_list; link; link = link->next) {
-		if (link->children) {
-			amdfam12_link_read_bases(dev, nodeid, link->link_num);
-		}
-	}
-
-	/*
-	 * This MMCONF resource must be reserved in the PCI domain.
-	 * It is not honored by the coreboot resource allocator if it is in
-	 * the CPU_CLUSTER.
-	 */
-	mmconf_resource(dev, MMIO_CONF_BASE);
-
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-
-static void set_resource(struct device *dev, struct resource *resource,
-			 u32 nodeid)
-{
-	resource_t rbase, rend;
-	unsigned int reg, link_num;
-	char buf[50];
-
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
-	/* Make certain the resource has actually been set */
-	if (!(resource->flags & IORESOURCE_ASSIGNED)) {
-		return;
-	}
-
-	/* If I have already stored this resource don't worry about it */
-	if (resource->flags & IORESOURCE_STORED) {
-		return;
-	}
-
-	/* Only handle PCI memory and IO resources */
-	if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
-		return;
-
-	/* Ensure I am actually looking at a resource of function 1 */
-	if ((resource->index & 0xffff) < 0x1000) {
-		return;
-	}
-	/* Get the base address */
-	rbase = resource->base;
-
-	/* Get the limit (rounded up) */
-	rend  = resource_end(resource);
-
-	/* Get the register and link */
-	reg  = resource->index & 0xfff; // 4k
-	link_num = IOINDEX_LINK(resource->index);
-
-	if (resource->flags & IORESOURCE_IO) {
-		set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8);
-	}
-	else if (resource->flags & IORESOURCE_MEM) {
-		set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1); // [39:8]
-	}
-	resource->flags |= IORESOURCE_STORED;
-	snprintf(buf, sizeof(buf), " <node %x link %x>", nodeid, link_num);
-	report_resource_stored(dev, resource, buf);
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-
-#if CONFIG(CONSOLE_VGA_MULTI)
-extern struct device *vga_pri;    // the primary vga device, defined in device.c
-#endif
-
-static void create_vga_resource(struct device *dev, unsigned int nodeid)
-{
-struct bus *link;
-
-printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
-	/* find out which link the VGA card is connected,
-	 * we only deal with the 'first' vga card */
-	for (link = dev->link_list; link; link = link->next) {
-		if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG(CONSOLE_VGA_MULTI)
-			printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
-					link->secondary,link->subordinate);
-			/* We need to make sure the vga_pri is under the link */
-			if ((vga_pri->bus->secondary >= link->secondary) &&
-			    (vga_pri->bus->secondary <= link->subordinate))
-#endif
-				break; // XXX this break looks questionable
-		}
-	}
-
-	/* no VGA card installed */
-	if (link == NULL)
-		return;
-
-	printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num);
-	set_vga_enable_reg(nodeid, link->link_num);
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-
-static void set_resources(struct device *dev)
-{
-	unsigned int nodeid;
-	struct bus *bus;
-	struct resource *res;
-
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
-	/* Find the nodeid */
-	nodeid = amdfam12_nodeid(dev);
-
-	create_vga_resource(dev, nodeid);
-
-	/* Set each resource we have found */
-	for (res = dev->resource_list; res; res = res->next) {
-		    set_resource(dev, res, nodeid);
-	}
-
-	for (bus = dev->link_list; bus; bus = bus->next) {
-		if (bus->children)
-			assign_resources(bus);
-	}
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-/* Domain/Root Complex related code */
-
-static void domain_read_resources(struct device *dev)
-{
-	unsigned int reg;
-
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
-	/* Find the already assigned resource pairs */
-	get_fx_devs();
-	for (reg = 0x80; reg <= 0xc0; reg+= 0x08) {
-		u32 base, limit;
-		base  = f1_read_config32(reg);
-		limit = f1_read_config32(reg + 0x04);
-		/* Is this register allocated? */
-		if ((base & 3) != 0) {
-			unsigned int nodeid, reg_link;
-			struct device *reg_dev;
-			if (reg < 0xc0) { // mmio
-				nodeid = (limit & 0xf) + (base&0x30);
-			} else { // io
-				nodeid =  (limit & 0xf) + ((base>>4)&0x30);
-			}
-			reg_link = (limit >> 4) & 7;
-			reg_dev = __f0_dev[nodeid];
-			if (reg_dev) {
-				/* Reserve the resource  */
-				struct resource *res;
-				res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
-				if (res) {
-					res->flags = 1;
-				}
-			}
-		}
-	}
-	/* FIXME: do we need to check extend conf space?
-	I don't believe that much preset value */
-
-	struct resource *resource;
-		/* Initialize the system-wide I/O space constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	resource->base  = 0x1000;
-	resource->limit = 0xffffUL;
-	resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED;
-
-	/* Initialize the system-wide memory resources constraints. */
-	resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	resource->base  = 0xc0000000ULL;
-	resource->limit = 0xdfffffffULL;
-	resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED;
-
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-
-static void domain_set_resources(struct device *dev)
-{
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-	printk(BIOS_DEBUG, "  amsr - incoming dev = %p\n", dev);
-
-	unsigned long mmio_basek;
-	u32 pci_tolm;
-	int idx;
-	struct bus *link;
-#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-	struct hw_mem_hole_info mem_hole;
-	u32 reset_memhole = 1;
-#endif
-
-	pci_tolm = 0xffffffffUL;
-	for (link = dev->link_list; link; link = link->next) {
-		pci_tolm = my_find_pci_tolm(link, pci_tolm);
-	}
-
-	// FIXME handle interleaved nodes. If you fix this here, please fix
-	// amdk8, too.
-	mmio_basek = pci_tolm >> 10;
-	/* Round mmio_basek to something the processor can support */
-	mmio_basek &= ~((1 << 6) -1);
-
-	// FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
-	// MMIO hole. If you fix this here, please fix amdk8, too.
-	/* Round the mmio hole to 64M */
-	mmio_basek &= ~((64*1024) - 1);
-
-#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-/* if the hw mem hole is already set in raminit stage, here we will compare
- * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will
- * use hole_basek as mmio_basek and we don't need to reset hole.
- * otherwise We reset the hole to the mmio_basek
- */
-
-	mem_hole = get_hw_mem_hole_info();
-
-	// Use hole_basek as mmio_basek, and we don't need to reset hole anymore
-	if ((mem_hole.node_id !=  -1) && (mmio_basek > mem_hole.hole_startk)) {
-		mmio_basek = mem_hole.hole_startk;
-		reset_memhole = 0;
-	}
-#endif
-
-	idx = 0x10;
-
-	struct dram_base_mask_t d;
-	resource_t basek, limitk, sizek; // 4 1T
-
-	d = get_dram_base_mask(0);
-
-	if (d.mask & 1) {
-		basek = ((resource_t)(d.base)) << 8;
-		limitk = (resource_t)((d.mask << 8) | 0xFFFFFF);
-		printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk);
-
-		/* Convert these values to multiples of 1K for ease of math. */
-		basek >>= 10;
-		limitk >>= 10;
-		sizek = limitk - basek + 1;
-
-		printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek);
-
-		/* see if we need a hole from 0xa0000 to 0xbffff */
-		if ((basek < 640) && (sizek > 768)) {
-			printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
-			ram_resource(dev, (idx | 0), basek, 640 - basek);
-			idx += 0x10;
-			basek = 768;
-			sizek = limitk - 768;
-		}
-
-		printk(BIOS_DEBUG,
-			"adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
-			 mmio_basek, basek, limitk);
-
-		/* split the region to accommodate pci memory space */
-		if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
-			if (basek <= mmio_basek) {
-				unsigned int pre_sizek;
-				pre_sizek = mmio_basek - basek;
-				if (pre_sizek > 0) {
-					ram_resource(dev, idx, basek, pre_sizek);
-					idx += 0x10;
-					sizek -= pre_sizek;
-				}
-				basek = mmio_basek;
-			}
-			if ((basek + sizek) <= 4*1024*1024) {
-				sizek = 0;
-			} else {
-				basek = 4*1024*1024;
-				sizek -= (4*1024*1024 - mmio_basek);
-			}
-		}
-
-		ram_resource(dev, (idx | 0), basek, sizek);
-		idx += 0x10;
-		printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
-		   0, mmio_basek, basek, limitk);
-	}
-	printk(BIOS_DEBUG, "  adsr - mmio_basek = %lx.\n", mmio_basek);
-
-	add_uma_resource_below_tolm(dev, 7);
-
-	for (link = dev->link_list; link; link = link->next) {
-		if (link->children)
-			assign_resources(link);
-	}
-	printk(BIOS_DEBUG, "  adsr - leaving this lovely routine.\n");
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-
-/* Bus related code */
-
-static void cpu_bus_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-	initialize_cpus(dev->link_list);
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-
-/* North Bridge Structures */
-
-
-static unsigned long acpi_fill_hest(acpi_hest_t *hest)
-{
-	void *addr, *current;
-
-	/* Skip the HEST header. */
-	current = (void *)(hest + 1);
-
-	addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE);
-	if (addr != NULL)
-		current += acpi_create_hest_error_source(hest, current, 0,
-				addr + 2, *(UINT16 *)addr - 2);
-
-	addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC);
-	if (addr != NULL)
-		current += acpi_create_hest_error_source(hest, current, 1,
-				addr + 2, *(UINT16 *)addr - 2);
-
-	return (unsigned long)current;
-}
-
-static void northbridge_fill_ssdt_generator(struct device *device)
-{
-	msr_t msr;
-	char pscope[] = "\\_SB.PCI0";
-
-	acpigen_write_scope(pscope);
-	msr = rdmsr(TOP_MEM);
-	acpigen_write_name_dword("TOM1", msr.lo);
-	msr = rdmsr(TOP_MEM2);
-	/*
-	 * Since XP only implements parts of ACPI 2.0, we can't use a qword
-	 * here.
-	 * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt
-	 * slide 22ff.
-	 * Shift value right by 20 bit to make it fit into 32bit,
-	 * giving us 1MB granularity and a limit of almost 4Exabyte of memory.
-	 */
-	acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
-	acpigen_pop_len();
-}
-
-static unsigned long agesa_write_acpi_tables(struct device *device,
-					     unsigned long current,
-					     acpi_rsdp_t *rsdp)
-{
-	acpi_srat_t *srat;
-	acpi_slit_t *slit;
-	acpi_header_t *ssdt;
-	acpi_hest_t *hest;
-
-	/* HEST */
-	current = ALIGN(current, 8);
-	hest = (acpi_hest_t *)current;
-	acpi_write_hest((void *)current, acpi_fill_hest);
-	acpi_add_table(rsdp, (void *)current);
-	current += ((acpi_header_t *)current)->length;
-
-	/* SRAT */
-	current = ALIGN(current, 8);
-	printk(BIOS_DEBUG, "ACPI:    * SRAT at %lx\n", current);
-	srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT);
-	if (srat != NULL) {
-		memcpy((void *)current, srat, srat->header.length);
-		srat = (acpi_srat_t *) current;
-		current += srat->header.length;
-		acpi_add_table(rsdp, srat);
-	}
-
-	/* SLIT */
-	current = ALIGN(current, 8);
-	printk(BIOS_DEBUG, "ACPI:   * SLIT at %lx\n", current);
-	slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT);
-	if (slit != NULL) {
-		memcpy((void *)current, slit, slit->header.length);
-		slit = (acpi_slit_t *) current;
-		current += slit->header.length;
-		acpi_add_table(rsdp, slit);
-	}
-
-	/* SSDT */
-	current = ALIGN(current, 16);
-	printk(BIOS_DEBUG, "ACPI:    * SSDT at %lx\n", current);
-	ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE);
-	if (ssdt != NULL) {
-		memcpy((void *)current, ssdt, ssdt->length);
-		ssdt = (acpi_header_t *) current;
-		current += ssdt->length;
-		acpi_add_table(rsdp,ssdt);
-	}
-
-	printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
-
-	return current;
-}
-
-
-static struct device_operations northbridge_operations = {
-	.read_resources   = read_resources,
-	.set_resources    = set_resources,
-	.acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator,
-	.write_acpi_tables = agesa_write_acpi_tables,
-	.enable_resources = pci_dev_enable_resources,
-	.init             = northbridge_init,
-	.enable           = 0,
-	.ops_pci          = 0,
-};
-
-
-static const struct pci_driver northbridge_driver __pci_driver = {
-	.ops = &northbridge_operations,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = 0x1705,
-};
-
-
-struct chip_operations northbridge_amd_agesa_family12_ops = {
-	CHIP_NAME("AMD Family 12h Northbridge")
-	.enable_dev = 0,
-};
-
-
-/* Root Complex Structures */
-
-
-static struct device_operations pci_domain_ops = {
-	.read_resources   = domain_read_resources,
-	.set_resources    = domain_set_resources,
-	.init             = DEVICE_NOOP,
-	.scan_bus         = pci_domain_scan_bus,
-};
-
-
-static struct device_operations cpu_bus_ops = {
-	.read_resources   = DEVICE_NOOP,
-	.set_resources    = DEVICE_NOOP,
-	.enable_resources = DEVICE_NOOP,
-	.init             = cpu_bus_init,
-	.scan_bus         = 0,
-};
-
-
-static void root_complex_enable_dev(struct device *dev)
-{
-	printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-	static int done = 0;
-
-	if (!done) {
-		setup_bsp_ramtop();
-		done = 1;
-	}
-
-	/* Set the operations if it is a special bus type */
-	if (dev->path.type == DEVICE_PATH_DOMAIN) {
-		dev->ops = &pci_domain_ops;
-	}
-	else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
-		dev->ops = &cpu_bus_ops;
-	}
-	printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
-}
-
-
-struct chip_operations northbridge_amd_agesa_family12_root_complex_ops = {
-	CHIP_NAME("AMD Family 12h Root Complex")
-	.enable_dev = root_complex_enable_dev,
-};
--- a/src/northbridge/amd/agesa/family12/state_machine.c
+++ b/src/northbridge/amd/agesa/family12/state_machine.c
@@ -1,87 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2016 Kyösti Mälkki
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <Porting.h>
-#include <AGESA.h>
-
-#include <cbmem.h>
-#include <northbridge/amd/agesa/state_machine.h>
-#include <northbridge/amd/agesa/agesa_helper.h>
-
-#include <sb_cimx.h>
-
-void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
-{
-}
-
-void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
-{
-}
-
-void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
-{
-}
-
-void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
-{
-	backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop);
-
-	sb_before_pci_init();
-}
-
-void platform_BeforeInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
-{
-	OemInitResume(&Resume->S3DataBlock);
-}
-
-void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume)
-{
-}
-
-void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
-{
-	EmptyHeap();
-}
-
-void platform_AfterInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env)
-{
-	sb_After_Pci_Init();
-}
-
-void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
-{
-	OemS3LateRestore(&S3Late->S3DataBlock);
-}
-
-void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late)
-{
-}
-
-void platform_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *Mid)
-{
-	sb_Mid_Post_Init();
-
-	amd_initcpuio();
-}
-
-void platform_AfterInitLate(struct sysinfo *cb, AMD_LATE_PARAMS *Late)
-{
-	sb_Late_Post();
-}
-
-void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save)
-{
-	OemS3Save(&S3Save->S3DataBlock);
-}
--- a/src/southbridge/amd/cimx/Kconfig
+++ b/src/southbridge/amd/cimx/Kconfig
@@ -18,4 +18,3 @@ config AMD_SB_CIMX
 	default n

 source src/southbridge/amd/cimx/sb800/Kconfig
-source src/southbridge/amd/cimx/sb900/Kconfig
--- a/src/southbridge/amd/cimx/Makefile.inc
+++ b/src/southbridge/amd/cimx/Makefile.inc
@@ -14,10 +14,7 @@
 #

 subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += sb800
-subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += sb900

 romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
-romstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c

 ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800) += cimx_util.c
-ramstage-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900) += cimx_util.c
--- a/src/southbridge/amd/cimx/sb900/Amd.h
+++ b/src/southbridge/amd/cimx/sb900/Amd.h
@@ -1,377 +0,0 @@
-/*****************************************************************************
- * AMD Generic Encapsulated Software Architecture                            */
-/**
- * @file
- *
- * Agesa structures and definitions
- *
- * Contains AMD AGESA/CIMx core interface
- *
- */
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * ***************************************************************************
- *
- */
-
-
-#ifndef _AMD_H_
-#define _AMD_H_
-
-// AGESA Types and Definitions
-#ifndef NULL
-  #define NULL 0
-#endif
-
-#define LAST_ENTRY 0xFFFFFFFF
-#define IOCF8 0xCF8
-#define IOCFC 0xCFC
-#define IN
-#define OUT
-
-#ifndef Int16FromChar
-#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
-#endif
-#ifndef Int32FromChar
-#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
-#endif
-
-#define IMAGE_SIGNATURE     Int32FromChar ('$', 'A', 'M', 'D')
-
-typedef unsigned int AGESA_STATUS;
-
-#define AGESA_SUCCESS       ((AGESA_STATUS) 0x0)
-#define AGESA_ALERT         ((AGESA_STATUS) 0x40000000)
-#define AGESA_WARNING       ((AGESA_STATUS) 0x40000001)
-#define AGESA_UNSUPPORTED   ((AGESA_STATUS) 0x80000003)
-#define AGESA_ERROR         ((AGESA_STATUS) 0xC0000001)
-#define AGESA_CRITICAL      ((AGESA_STATUS) 0xC0000002)
-#define AGESA_FATAL         ((AGESA_STATUS) 0xC0000003)
-
-typedef AGESA_STATUS(*CALLOUT_ENTRY) (unsigned int Param1, unsigned int Param2,
-				       void *ConfigPtr);
-typedef AGESA_STATUS(*IMAGE_ENTRY) (IN OUT void *ConfigPtr);
-typedef AGESA_STATUS(*MODULE_ENTRY) (IN OUT void *ConfigPtr);
-
-///This allocation type is used by the AmdCreateStruct entry point
-typedef enum {
-  PreMemHeap = 0,                                           ///< Create heap in cache.
-  PostMemDram,                                              ///< Create heap in memory.
-  ByHost                                                    ///< Create heap by Host.
-} ALLOCATION_METHOD;
-
-/// These width descriptors are used by the library function, and others, to specify the data size
-typedef enum ACCESS_WIDTH {
-  AccessWidth8 = 1,                                         ///< Access width is 8 bits.
-  AccessWidth16,                                            ///< Access width is 16 bits.
-  AccessWidth32,                                            ///< Access width is 32 bits.
-  AccessWidth64,                                            ///< Access width is 64 bits.
-
-  AccessS3SaveWidth8 = 0x81,                                ///< Save 8 bits data.
-  AccessS3SaveWidth16,                                      ///< Save 16 bits data.
-  AccessS3SaveWidth32,                                      ///< Save 32 bits data.
-  AccessS3SaveWidth64,                                      ///< Save 64 bits data.
-} ACCESS_WIDTH;
-
-// AGESA Structures
-
-/// The standard header for all AGESA services.
-typedef struct _AMD_CONFIG_PARAMS {
-  IN       unsigned int          ImageBasePtr;     ///< The AGESA Image base address.
-  IN       unsigned int          Func;             ///< The service desired, @sa dispatch.h.
-  IN       unsigned int          AltImageBasePtr;  ///< Alternate Image location
-  IN       unsigned int          PcieBasePtr;      ///< PCIe MMIO Base address, if configured.
-  union {                                    ///< Callback pointer
-    IN       unsigned long long          PlaceHolder;    ///< Place holder
-    IN       CALLOUT_ENTRY   CalloutPtr;     ///< For Callout from AGESA
-  } CALLBACK;
-  IN OUT   unsigned int          Reserved[2];      ///< This space is reserved for future use.
-} AMD_CONFIG_PARAMS;
-
-
-/// AGESA Binary module header structure
-typedef struct _AMD_IMAGE_HEADER {
-  IN       unsigned int  Signature;                          ///< Binary Signature
-  IN       signed char   CreatorID[8];                       ///< 8 characters ID
-  IN       signed char   Version[12];                        ///< 12 characters version
-  IN       unsigned int  ModuleInfoOffset;                   ///< Offset of module
-  IN       unsigned int  EntryPointAddress;                  ///< Entry address
-  IN       unsigned int  ImageBase;                          ///< Image base
-  IN       unsigned int  RelocTableOffset;                   ///< Relocate Table offset
-  IN       unsigned int  ImageSize;                          ///< Size
-  IN       unsigned short  Checksum;                           ///< Checksum
-  IN       unsigned char   ImageType;                          ///< Type
-  IN       unsigned char   V_Reserved;                         ///< Reserved
-} AMD_IMAGE_HEADER;
-
-/// AGESA Binary module header structure
-typedef struct _AMD_MODULE_HEADER {
-  IN       unsigned int          ModuleHeaderSignature;      ///< Module signature
-  IN       signed char           ModuleIdentifier[8];        ///< 8 characters ID
-  IN       signed char           ModuleVersion[12];          ///< 12 characters version
-  IN       MODULE_ENTRY    ModuleDispatcherPtr;        ///< A pointer point to dispatcher
-  IN       struct _AMD_MODULE_HEADER  *NextBlockPtr;    ///< Next module header link
-} AMD_MODULE_HEADER;
-
-#define FUNC_0    0   // bit-placed for PCI address creation
-#define FUNC_1    1
-#define FUNC_2    2
-#define FUNC_3    3
-#define FUNC_4    4
-#define FUNC_5    5
-#define FUNC_6    6
-#define FUNC_7    7
-
-//   SBDFO - Segment Bus Device Function Offset
-//   31:28   Segment (4-bits)
-//   27:20   Bus     (8-bits)
-//   19:15   Device  (5-bits)
-//   14:12   Function (3-bits)
-//   11:00   Offset  (12-bits)
-
-#if 0
-#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((unsigned int) (Seg)) << 28) | (((unsigned int) (Bus)) << 20) | \
-                   (((unsigned int) (Dev)) << 15) | (((unsigned int) (Fun)) << 12) | ((unsigned int) (Off)))
-#endif
-#define ILLEGAL_SBDFO 0xFFFFFFFF
-
-/*
-/// CPUID data received registers format
-typedef struct _SB_CPUID_DATA {
-  IN OUT   unsigned int          EAX_Reg;                ///< CPUID instruction result in EAX
-  IN OUT   unsigned int          EBX_Reg;                ///< CPUID instruction result in EBX
-  IN OUT   unsigned int          ECX_Reg;                ///< CPUID instruction result in ECX
-  IN OUT   unsigned int          EDX_Reg;                ///< CPUID instruction result in EDX
-} SB_CPUID_DATA;
-*/
-
-#define WARM_RESET 1
-#define COLD_RESET 2      // Cold reset
-#define RESET_CPU  4      // Triggers a CPU reset
-
-/// HT frequency for external callbacks
-typedef enum {
-  HT_FREQUENCY_200M          = 0,                 ///< HT speed 200 for external callbacks
-  HT_FREQUENCY_400M          = 2,                 ///< HT speed 400 for external callbacks
-  HT_FREQUENCY_600M          = 4,                 ///< HT speed 600 for external callbacks
-  HT_FREQUENCY_800M          = 5,                 ///< HT speed 800 for external callbacks
-  HT_FREQUENCY_1000M         = 6,                 ///< HT speed 1000 for external callbacks
-  HT_FREQUENCY_1200M         = 7,                 ///< HT speed 1200 for external callbacks
-  HT_FREQUENCY_1400M         = 8,                 ///< HT speed 1400 for external callbacks
-  HT_FREQUENCY_1600M         = 9,                 ///< HT speed 1600 for external callbacks
-  HT_FREQUENCY_1800M         = 10,                ///< HT speed 1800 for external callbacks
-  HT_FREQUENCY_2000M         = 11,                ///< HT speed 2000 for external callbacks
-  HT_FREQUENCY_2200M         = 12,                ///< HT speed 2200 for external callbacks
-  HT_FREQUENCY_2400M         = 13,                ///< HT speed 2400 for external callbacks
-  HT_FREQUENCY_2600M         = 14,                ///< HT speed 2600 for external callbacks
-  HT_FREQUENCY_2800M         = 17,                ///< HT speed 2800 for external callbacks
-  HT_FREQUENCY_3000M         = 18,                ///< HT speed 3000 for external callbacks
-  HT_FREQUENCY_3200M         = 19                 ///< HT speed 3200 for external callbacks
-} HT_FREQUENCIES;
-
-#ifndef BIT0
-  #define BIT0        0x0000000000000001ull
-#endif
-#ifndef BIT1
-  #define BIT1        0x0000000000000002ull
-#endif
-#ifndef BIT2
-  #define BIT2        0x0000000000000004ull
-#endif
-#ifndef BIT3
-  #define BIT3        0x0000000000000008ull
-#endif
-#ifndef BIT4
-  #define BIT4        0x0000000000000010ull
-#endif
-#ifndef BIT5
-  #define BIT5        0x0000000000000020ull
-#endif
-#ifndef BIT6
-  #define BIT6        0x0000000000000040ull
-#endif
-#ifndef BIT7
-  #define BIT7        0x0000000000000080ull
-#endif
-#ifndef BIT8
-  #define BIT8        0x0000000000000100ull
-#endif
-#ifndef BIT9
-  #define BIT9        0x0000000000000200ull
-#endif
-#ifndef BIT10
-  #define BIT10       0x0000000000000400ull
-#endif
-#ifndef BIT11
-  #define BIT11       0x0000000000000800ull
-#endif
-#ifndef BIT12
-  #define BIT12       0x0000000000001000ull
-#endif
-#ifndef BIT13
-  #define BIT13       0x0000000000002000ull
-#endif
-#ifndef BIT14
-  #define BIT14       0x0000000000004000ull
-#endif
-#ifndef BIT15
-  #define BIT15       0x0000000000008000ull
-#endif
-#ifndef BIT16
-  #define BIT16       0x0000000000010000ull
-#endif
-#ifndef BIT17
-  #define BIT17       0x0000000000020000ull
-#endif
-#ifndef BIT18
-  #define BIT18       0x0000000000040000ull
-#endif
-#ifndef BIT19
-  #define BIT19       0x0000000000080000ull
-#endif
-#ifndef BIT20
-  #define BIT20       0x0000000000100000ull
-#endif
-#ifndef BIT21
-  #define BIT21       0x0000000000200000ull
-#endif
-#ifndef BIT22
-  #define BIT22       0x0000000000400000ull
-#endif
-#ifndef BIT23
-  #define BIT23       0x0000000000800000ull
-#endif
-#ifndef BIT24
-  #define BIT24       0x0000000001000000ull
-#endif
-#ifndef BIT25
-  #define BIT25       0x0000000002000000ull
-#endif
-#ifndef BIT26
-  #define BIT26       0x0000000004000000ull
-#endif
-#ifndef BIT27
-  #define BIT27       0x0000000008000000ull
-#endif
-#ifndef BIT28
-  #define BIT28       0x0000000010000000ull
-#endif
-#ifndef BIT29
-  #define BIT29       0x0000000020000000ull
-#endif
-#ifndef BIT30
-  #define BIT30       0x0000000040000000ull
-#endif
-#ifndef BIT31
-  #define BIT31       0x0000000080000000ull
-#endif
-#ifndef BIT32
-  #define BIT32       0x0000000100000000ull
-#endif
-#ifndef BIT33
-  #define BIT33       0x0000000200000000ull
-#endif
-#ifndef BIT34
-  #define BIT34       0x0000000400000000ull
-#endif
-#ifndef BIT35
-  #define BIT35       0x0000000800000000ull
-#endif
-#ifndef BIT36
-  #define BIT36       0x0000001000000000ull
-#endif
-#ifndef BIT37
-  #define BIT37       0x0000002000000000ull
-#endif
-#ifndef BIT38
-  #define BIT38       0x0000004000000000ull
-#endif
-#ifndef BIT39
-  #define BIT39       0x0000008000000000ull
-#endif
-#ifndef BIT40
-  #define BIT40       0x0000010000000000ull
-#endif
-#ifndef BIT41
-  #define BIT41       0x0000020000000000ull
-#endif
-#ifndef BIT42
-  #define BIT42       0x0000040000000000ull
-#endif
-#ifndef BIT43
-  #define BIT43       0x0000080000000000ull
-#endif
-#ifndef BIT44
-  #define BIT44       0x0000100000000000ull
-#endif
-#ifndef BIT45
-  #define BIT45       0x0000200000000000ull
-#endif
-#ifndef BIT46
-  #define BIT46       0x0000400000000000ull
-#endif
-#ifndef BIT47
-  #define BIT47       0x0000800000000000ull
-#endif
-#ifndef BIT48
-  #define BIT48       0x0001000000000000ull
-#endif
-#ifndef BIT49
-  #define BIT49       0x0002000000000000ull
-#endif
-#ifndef BIT50
-  #define BIT50       0x0004000000000000ull
-#endif
-#ifndef BIT51
-  #define BIT51       0x0008000000000000ull
-#endif
-#ifndef BIT52
-  #define BIT52       0x0010000000000000ull
-#endif
-#ifndef BIT53
-  #define BIT53       0x0020000000000000ull
-#endif
-#ifndef BIT54
-  #define BIT54       0x0040000000000000ull
-#endif
-#ifndef BIT55
-  #define BIT55       0x0080000000000000ull
-#endif
-#ifndef BIT56
-  #define BIT56       0x0100000000000000ull
-#endif
-#ifndef BIT57
-  #define BIT57       0x0200000000000000ull
-#endif
-#ifndef BIT58
-  #define BIT58       0x0400000000000000ull
-#endif
-#ifndef BIT59
-  #define BIT59       0x0800000000000000ull
-#endif
-#ifndef BIT60
-  #define BIT60       0x1000000000000000ull
-#endif
-#ifndef BIT61
-  #define BIT61       0x2000000000000000ull
-#endif
-#ifndef BIT62
-  #define BIT62       0x4000000000000000ull
-#endif
-#ifndef BIT63
-  #define BIT63       0x8000000000000000ull
-#endif
-#endif
--- a/src/southbridge/amd/cimx/sb900/AmdSbLib.h
+++ b/src/southbridge/amd/cimx/sb900/AmdSbLib.h
@@ -1,160 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * ***************************************************************************
- *
- */
-
-#ifndef _AMD_SB_LIB_H_
-#define _AMD_SB_LIB_H_
-
-#include <console/vtxprintf.h>
-
-#pragma pack (push, 1)
-
-#define IMAGE_ALIGN          32*1024
-#define NUM_IMAGE_LOCATION   32
-
-//Entry Point Call
-typedef void (*CIM_IMAGE_ENTRY) (void *pConfig);
-
-//Hook Call
-
-typedef struct _CIMFILEHEADER
-{
-  unsigned int  AMDLogo;
-  unsigned long long  CreatorID;
-  unsigned int  Version1;
-  unsigned int  Version2;
-  unsigned int  Version3;
-  unsigned int  ModuleInfoOffset;
-  unsigned int  EntryPoint;
-  unsigned int  ImageBase;
-  unsigned int  RelocTableOffset;
-  unsigned int  ImageSize;
-  unsigned short  CheckSum;
-  unsigned char ImageType;
-  unsigned char Reserved2;
-} CIMFILEHEADER;
-
-#ifndef BIT0
-  #define BIT0 (1 << 0)
-#endif
-#ifndef BIT1
-  #define BIT1 (1 << 1)
-#endif
-#ifndef BIT2
-  #define BIT2 (1 << 2)
-#endif
-#ifndef BIT3
-  #define BIT3 (1 << 3)
-#endif
-#ifndef BIT4
-  #define BIT4 (1 << 4)
-#endif
-#ifndef BIT5
-  #define BIT5 (1 << 5)
-#endif
-#ifndef BIT6
-  #define BIT6 (1 << 6)
-#endif
-#ifndef BIT7
-  #define BIT7 (1 << 7)
-#endif
-#ifndef BIT8
-  #define BIT8 (1 << 8)
-#endif
-#ifndef BIT9
-  #define BIT9 (1 << 9)
-#endif
-#ifndef BIT10
-  #define BIT10 (1 << 10)
-#endif
-#ifndef BIT11
-  #define BIT11 (1 << 11)
-#endif
-#ifndef BIT12
-  #define BIT12 (1 << 12)
-#endif
-#ifndef BIT13
-  #define BIT13 (1 << 13)
-#endif
-#ifndef BIT14
-  #define BIT14 (1 << 14)
-#endif
-#ifndef BIT15
-  #define BIT15 (1 << 15)
-#endif
-#ifndef BIT16
-  #define BIT16 (1 << 16)
-#endif
-#ifndef BIT17
-  #define BIT17 (1 << 17)
-#endif
-#ifndef BIT18
-  #define BIT18 (1 << 18)
-#endif
-#ifndef BIT19
-  #define BIT19 (1 << 19)
-#endif
-#ifndef BIT20
-  #define BIT20 (1 << 20)
-#endif
-#ifndef BIT21
-  #define BIT21 (1 << 21)
-#endif
-#ifndef BIT22
-  #define BIT22 (1 << 22)
-#endif
-#ifndef BIT23
-  #define BIT23 (1 << 23)
-#endif
-#ifndef  BIT24
-  #define BIT24 (1 << 24)
-#endif
-#ifndef BIT25
-  #define BIT25 (1 << 25)
-#endif
-#ifndef BIT26
-  #define BIT26 (1 << 26)
-#endif
-#ifndef BIT27
-  #define BIT27 (1 << 27)
-#endif
-#ifndef BIT28
-  #define BIT28 (1 << 28)
-#endif
-#ifndef BIT29
-  #define BIT29 (1 << 29)
-#endif
-#ifndef BIT30
-  #define BIT30 (1 << 30)
-#endif
-#ifndef BIT31
-  #define BIT31 (1 << 31)
-#endif
-
-#pragma pack (pop)
-
-typedef enum
-{
-  AccWidthUint8 = 0,
-  AccWidthUint16,
-  AccWidthUint32,
-} ACC_WIDTH;
-
-#define S3_SAVE  0x80
-
-#endif
--- a/src/southbridge/amd/cimx/sb900/Kconfig
+++ b/src/southbridge/amd/cimx/sb900/Kconfig
@@ -1,54 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2011 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-config SOUTHBRIDGE_AMD_CIMX_SB900
-	bool
-	default n
-	select IOAPIC
-	select AMD_SB_CIMX
-	select HAVE_CF9_RESET
-	select HAVE_CF9_RESET_PREPARE
-
-if SOUTHBRIDGE_AMD_CIMX_SB900
-config SATA_CONTROLLER_MODE
-	hex
-	default 0x0
-	help
-	  0x0 = Native IDE mode.
-	  0x1 = RAID mode.
-	  0x2 = AHCI mode.
-	  0x3 = Legacy IDE mode.
-	  0x4 = IDE->AHCI mode.
-	  0x5 = AHCI mode as 7804 ID (AMD driver).
-	  0x6 = IDE->AHCI mode as 7804 ID (AMD driver).
-
-config PCIB_ENABLE
-	bool
-	default n
-	help
-	  n = Disable PCI Bridge Device 14 Function 4.
-	  y = Enable PCI Bridge Device 14 Function 4.
-
-config ACPI_SCI_IRQ
-	hex
-	default 0x9
-	help
-	  Set SCI IRQ to 9.
-
-config BOOTBLOCK_SOUTHBRIDGE_INIT
-	string
-	default "southbridge/amd/cimx/sb900/bootblock.c"
-
-endif #SOUTHBRIDGE_AMD_CIMX_SB900
--- a/src/southbridge/amd/cimx/sb900/Makefile.inc
+++ b/src/southbridge/amd/cimx/sb900/Makefile.inc
@@ -1,34 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2011 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-
-# SB900 Platform Files
-
-romstage-y += cfg.c
-romstage-y += early.c
-romstage-y += smbus.c smbus_spd.c
-romstage-y += reset.c
-romstage-y += ramtop.c
-
-postcar-y += ramtop.c
-
-ramstage-y += cfg.c
-ramstage-y += early.c
-ramstage-y += late.c
-ramstage-y += reset.c
-ramstage-y += ramtop.c
-
-ramstage-y   += smbus.c
-ramstage-y   += lpc.c
--- a/src/southbridge/amd/cimx/sb900/SbPlatform.h
+++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h
@@ -1,148 +0,0 @@
-/*
- *****************************************************************************
- *
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * ***************************************************************************
- *
- */
-
-#ifndef _AMD_SBPLATFORM_H_
-#define _AMD_SBPLATFORM_H_
-
-#include <stddef.h>
-
-typedef unsigned long long PLACEHOLDER;
-
-#ifndef SBOEM_ACPI_RESTORE_SWSMI
-  #define SBOEM_BEFORE_PCI_RESTORE_SWSMI    0xD3
-  #define SBOEM_AFTER_PCI_RESTORE_SWSMI     0xD4
-#endif
-
-#ifndef _AMD_NB_CIM_X_PROTOCOL_H_
-
-/*
-/// Extended PCI Address
-typedef struct _EXT_PCI_ADDR {
-  UINT32                  Reg :16; ///< / PCI Register
-  UINT32                  Func:3;  ///< / PCI Function
-  UINT32                  Dev :5;  ///< / PCI Device
-  UINT32                  Bus :8;  ///< / PCI Address
-} EXT_PCI_ADDR;
-
-/// PCI Address
-typedef union _PCI_ADDR {
-  UINT32                  ADDR; ///< / 32 bit Address
-  EXT_PCI_ADDR            Addr; ///< / Extended PCI Address
-} PCI_ADDR;
-*/
-#endif
-#define FIXUP_PTR(ptr)  ptr
-
-#include "AmdSbLib.h"
-#include "Amd.h"
-#include "Hudson-2.h"
-#include "SbType.h"
-#include "AcpiLib.h"
-#include "SbDef.h"
-#include "SbSubFun.h"
-#include "platform_cfg.h"	/* mainboard specific configuration */
-#include <OEM.h>		/* platform default configuration */
-#include <AMD.h>
-#include "SbBiosRamUsage.h"
-#include "EcFan.h"
-
-//------------------------------------------------------------------------------------------------------------------------//
-/**
- * SB_CIMx_PARAMETER                0                1                   2            Default Value When CIMx Take over
- *  SpreadSpectrum         CIMx take over   User (Setup Option) User (Setup Option)               Enable
- * SpreadSpectrumType      CIMx take over   User (Setup Option) User (Setup Option)               Normal
- *     HpetTimer           CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *     HpetMsiDis          CIMx take over   User (Setup Option) User (Setup Option)               Enable (0x00)
- *      IrConfig           CIMx take over   User (Setup Option) User (Setup Option)               Disable (0x00)
- * SpiFastReadEnable       CIMx take over   User (Setup Option) User (Setup Option)               Disable
- * SpiFastReadSpeed        CIMx take over   User (Setup Option) User (Setup Option)               Disable (NULL)
- *     NbSbGen2            CIMx take over   User (Setup Option) User (Setup Option)               Enable
- * AlinkPhyPllPowerDown    CIMx take over   User (Setup Option) User (Setup Option)               Enable
- * ResetCpuOnSyncFlood     CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *     GppGen2             CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  GppMemWrImprove        CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *    GppPortAspm          CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  GppLaneReversal        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  GppPhyPllPowerDown     CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *  UsbPhyPowerDown        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  SBGecDebugBus          CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *     SBGecPwr            CIMx take over   User (Setup Option) User (Setup Option)               Never Power down (0x11)
- *   SataSetMaxGen2        CIMx take over   User (Setup Option) User (Setup Option)               Max Gen3 (0x00)
- *   SataClkMode           CIMx take over   User (Setup Option) User (Setup Option)               0x90   int. 100Mhz
- *  SataAggrLinkPmCap      CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *  SataPortMultCap        CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *   SataPscCap            CIMx take over   User (Setup Option) User (Setup Option)               Enable (0x00)
- *   SataSscCap            CIMx take over   User (Setup Option) User (Setup Option)               Enable (0x00)
- * SataFisBasedSwitching   CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *   SataCccSupport        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *   SataMsiCapability     CIMx take over   User (Setup Option) User (Setup Option)               Enable
- *   SataClkAutoOff        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *    AcDcMsg              CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *   TimerTickTrack        CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  ClockInterruptTag      CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  OhciTrafficHanding     CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  EhciTrafficHanding     CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *  FusionMsgCMultiCore    CIMx take over   User (Setup Option) User (Setup Option)               Disable
- *   FusionMsgCStage       CIMx take over   User (Setup Option) User (Setup Option)               Disable
- */
-#define SB_CIMx_PARAMETER		0x02
-
-// Generic
-#define cimSpreadSpectrumDefault	TRUE
-#define cimSpreadSpectrumTypeDefault	0x00      // Normal
-#define cimHpetTimerDefault		TRUE
-#define cimHpetMsiDisDefault		FALSE     // Enable
-#define cimIrConfigDefault		0x00      // Disable
-#define cimSpiFastReadEnableDefault	0x00      // Disable
-#define cimSpiFastReadSpeedDefault	0x00      // NULL
-// GPP/AB Controller
-#define cimNbSbGen2Default		TRUE
-#define cimAlinkPhyPllPowerDownDefault	TRUE
-#define cimResetCpuOnSyncFloodDefault	TRUE
-#define cimGppGen2Default		FALSE
-#define cimGppMemWrImproveDefault	TRUE
-#define cimGppPortAspmDefault		FALSE
-#define cimGppLaneReversalDefault	FALSE
-#define cimGppPhyPllPowerDownDefault	TRUE
-// USB Controller
-#define cimUsbPhyPowerDownDefault	FALSE
-// GEC Controller
-#define cimSBGecDebugBusDefault		FALSE
-#define cimSBGecPwrDefault		0x03
-// Sata Controller
-#define cimSataSetMaxGen2Default	0x00
-#define cimSATARefClkSelDefault		0x10
-#define cimSATARefDivSelDefault		0x80
-#define cimSataAggrLinkPmCapDefault	TRUE
-#define cimSataPortMultCapDefault	TRUE
-#define cimSataPscCapDefault		0x00      // Enable
-#define cimSataSscCapDefault		0x00      // Enable
-#define cimSataFisBasedSwitchingDefault	FALSE
-#define cimSataCccSupportDefault	FALSE
-#define cimSataClkAutoOffDefault	FALSE
-#define cimNativepciesupportDefault	FALSE
-// Fusion Related
-#define cimAcDcMsgDefault		FALSE
-#define cimTimerTickTrackDefault	FALSE
-#define cimClockInterruptTagDefault	FALSE
-#define cimOhciTrafficHandingDefault	FALSE
-#define cimEhciTrafficHandingDefault	FALSE
-#define cimFusionMsgCMultiCoreDefault	FALSE
-#define cimFusionMsgCStageDefault	FALSE
-#endif // _AMD_SBPLATFORM_H_
--- a/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h
+++ b/src/southbridge/amd/cimx/sb900/amd_pci_int_defs.h
@@ -1,70 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef AMD_PCI_INT_DEFS_H
-#define AMD_PCI_INT_DEFS_H
-
-/*
- * PIRQ and device routing - these define the index
- * into the FCH PCI_INTR 0xC00/0xC01 interrupt
- * routing table
- */
-#define FCH_INT_TABLE_SIZE 0x54
-
-#define PIRQ_NC		0x1F	/* Not Used */
-#define PIRQ_A		0x00	/* INT A */
-#define PIRQ_B		0x01	/* INT B */
-#define PIRQ_C		0x02	/* INT C */
-#define PIRQ_D		0x03	/* INT D */
-#define PIRQ_E		0x04	/* INT E */
-#define PIRQ_F		0x05	/* INT F */
-#define PIRQ_G		0x06	/* INT G */
-#define PIRQ_H		0x07	/* INT H */
-#define PIRQ_MISC	0x08	/* Miscellaneous IRQ Settings - See FCH Spec */
-#define PIRQ_MISC0	0x09	/* Miscellaneous0 IRQ Settings */
-#define PIRQ_MISC1	0x0A	/* Miscellaneous1 IRQ Settings */
-#define PIRQ_MISC2	0x0B	/* Miscellaneous2 IRQ Settings */
-#define PIRQ_SIRQA	0x0C	/* Serial IRQ INTA */
-#define PIRQ_SIRQB	0x0D	/* Serial IRQ INTA */
-#define PIRQ_SIRQC	0x0E	/* Serial IRQ INTA */
-#define PIRQ_SIRQD	0x0F	/* Serial IRQ INTA */
-#define PIRQ_SCI	0x10	/* SCI IRQ */
-#define PIRQ_SMBUS	0x11	/* SMBUS	14h.0 */
-#define PIRQ_ASF	0x12	/* ASF */
-#define PIRQ_HDA	0x13	/* HDA		14h.2 */
-#define PIRQ_FC		0x14	/* FC */
-#define PIRQ_GEC	0x15	/* GEC */
-#define PIRQ_PMON	0x16	/* Performance Monitor */
-#define PIRQ_IMC0	0x20	/* IMC INT0 */
-#define PIRQ_IMC1	0x21	/* IMC INT1 */
-#define PIRQ_IMC2	0x22	/* IMC INT2 */
-#define PIRQ_IMC3	0x23	/* IMC INT3 */
-#define PIRQ_IMC4	0x24	/* IMC INT4 */
-#define PIRQ_IMC5	0x25	/* IMC INT5 */
-#define PIRQ_OHCI1	0x30	/* USB OHCI	12h.0 */
-#define PIRQ_EHCI1	0x31	/* USB EHCI	12h.2 */
-#define PIRQ_OHCI2	0x32	/* USB OHCI	13h.0 */
-#define PIRQ_EHCI2	0x33	/* USB EHCI	13h.2 */
-#define PIRQ_OHCI3	0x34	/* USB OHCI	16h.0 */
-#define PIRQ_EHCI3	0x35	/* USB EHCI	16h.2 */
-#define PIRQ_OHCI4	0x36	/* USB OHCI	14h.5 */
-#define PIRQ_IDE	0x40	/* IDE		14h.1 */
-#define PIRQ_SATA	0x41	/* SATA		11h.0 */
-#define PIRQ_GPP0	0x50	/* GPP INT 0 */
-#define PIRQ_GPP1	0x51	/* GPP INT 1 */
-#define PIRQ_GPP2	0x52	/* GPP INT 2 */
-#define PIRQ_GPP3	0x53	/* GPP INT 3 */
-
-#endif /* AMD_PCI_INT_DEFS_H */
--- a/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h
+++ b/src/southbridge/amd/cimx/sb900/amd_pci_int_types.h
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef AMD_PCI_INT_TYPES_H
-#define AMD_PCI_INT_TYPES_H
-
-const char *intr_types[] = {
-	[0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t",
-	[0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD",
-	[0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "FC\t\t", "GEC\t", "PerMon\t",
-	[0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t",
-	[0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC",
-	[0x40] = "IDE\t", "SATA\t",
-	[0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t"
-};
-
-#endif /* AMD_PCI_INT_TYPES_H */
--- a/src/southbridge/amd/cimx/sb900/bootblock.c
+++ b/src/southbridge/amd/cimx/sb900/bootblock.c
@@ -1,58 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci_ops.h>
-
-static void sb900_enable_rom(void)
-{
-  u32 word;
-  u32 dword;
-  pci_devfn_t dev;
-
-  dev = PCI_DEV(0, 0x14, 0x03);
-  /* SB900 LPC Bridge 0:20:3:44h.
-   * BIT6: Port Enable for serial port 0x3f8-0x3ff
-   * BIT29: Port Enable for KBC port 0x60 and 0x64
-   * BIT30: Port Enable for ACPI Micro-Controller port 0x66 and 0x62
-   */
-  dword = pci_io_read_config32(dev, 0x44);
-  //dword |= (1<<6) | (1<<29) | (1<<30);
-  /*Turn on all of LPC IO Port decode enable */
-  dword = 0xffffffff;
-  pci_io_write_config32(dev, 0x44, dword);
-
-  /* SB900 LPC Bridge 0:20:3:48h.
-   * BIT0: Port Enable for SuperIO 0x2E-0x2F
-   * BIT1: Port Enable for SuperIO 0x4E-0x4F
-   * BIT4: Port Enable for LPC ROM Address Arrage2 (0x68-0x6C)
-   * BIT6: Port Enable for RTC IO 0x70-0x73
-   * BIT21: Port Enable for Port 0x80
-   */
-  dword = pci_io_read_config32(dev, 0x48);
-  dword |= (1<<0) | (1<<1) | (1<<4) | (1<<6) | (1<<21);
-  pci_io_write_config32(dev, 0x48, dword);
-
-  /* Enable 4MB ROM access at 0xFFE00000 - 0xFFFFFFFF */
-  /* Set the 4MB enable bits */
-  word = pci_io_read_config16(dev, 0x6c);
-  word = 0xFFC0;
-  pci_io_write_config16(dev, 0x6c, word);
-}
-
-static void bootblock_southbridge_init(void)
-{
-  /* Setup the ROM access for 2M */
-  sb900_enable_rom();
-}
--- a/src/southbridge/amd/cimx/sb900/cfg.c
+++ b/src/southbridge/amd/cimx/sb900/cfg.c
@@ -1,298 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <string.h>
-
-#include "SbPlatform.h"
-#include "platform_cfg.h"
-
-/**
- * @brief South Bridge CIMx configuration
- *
- * should be called before execute CIMx function.
- * this function will be called in romstage and ramstage.
- */
-void sb900_cimx_config(AMDSBCFG *sb_config)
-{
-	if (!sb_config) {
-	printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
-		return;
-	}
-    printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
-	memset(sb_config, 0, sizeof(AMDSBCFG));
-
-	/* static Build Parameters */
-	sb_config->BuildParameters.BiosSize				= BIOS_SIZE;
-	sb_config->BuildParameters.LegacyFree			= LEGACY_FREE;
-	sb_config->BuildParameters.WatchDogTimerBase	= WATCHDOG_TIMER_BASE_ADDRESS;	// Board Level
-	sb_config->BuildParameters.AcpiGpe0BlkAddr		= GPE0_BLK_ADDRESS;				// Board Level
-	sb_config->BuildParameters.CpuControlBlkAddr	= CPU_CNT_BLK_ADDRESS;			// Board Level
-	sb_config->BuildParameters.AcpiPmTmrBlkAddr		= PM1_TMR_BLK_ADDRESS;			// Board Level
-	sb_config->BuildParameters.AcpiPm1CntBlkAddr	= PM1_CNT_BLK_ADDRESS;			// Board Level
-	sb_config->BuildParameters.AcpiPm1EvtBlkAddr	= PM1_EVT_BLK_ADDRESS;			// Board Level
-	sb_config->BuildParameters.SioPmeBaseAddress	= SIO_PME_BASE_ADDRESS;			// Board Level
-	sb_config->BuildParameters.SpiRomBaseAddress	= SPI_BASE_ADDRESS;				// Board Level
-	sb_config->BuildParameters.Smbus0BaseAddress	= SMBUS0_BASE_ADDRESS;			// Board Level
-	sb_config->BuildParameters.Smbus1BaseAddress	= SMBUS1_BASE_ADDRESS;			// Board Level
-
-	/* Turn on CDROM and HDD Power */
-	sb_config->SATAMODE.SataMode.SataClkMode		= SATA_CLK_RESERVED;
-
-	// header
-	sb_config->StdHeader.PcieBasePtr				= PCIEX_BASE_ADDRESS;
-
-	// Build Parameters
-	sb_config->BuildParameters.ImcEnableOverWrite	= IMC_ENABLE_OVER_WRITE;		// Internal Option
-	sb_config->BuildParameters.UsbMsi				= USB_MSI;						// Internal Option
-	sb_config->BuildParameters.HdAudioMsi			= HDAUDIO_MSI;					// Internal Option
-	sb_config->BuildParameters.LpcMsi				= LPC_MSI;						// Internal Option
-	sb_config->BuildParameters.PcibMsi				= PCIB_MSI;						// Internal Option
-	sb_config->BuildParameters.AbMsi				= AB_MSI;						// Internal Option
-	sb_config->BuildParameters.GecShadowRomBase		= GEC_SHADOWROM_BASE;			// Board Level
-	sb_config->BuildParameters.HpetBase				= HPET_BASE_ADDRESS;			// Board Level
-	sb_config->BuildParameters.SataIDESsid			= SATA_IDE_MODE_SSID;			// Board Level
-	sb_config->BuildParameters.SataRAIDSsid			= SATA_RAID_MODE_SSID;			// Board Level
-	sb_config->BuildParameters.SataRAID5Ssid		= SATA_RAID5_MODE_SSID;			// Board Level
-	sb_config->BuildParameters.SataAHCISsid			= SATA_AHCI_SSID;				// Board Level
-	sb_config->BuildParameters.OhciSsid				= OHCI_SSID;					// Board Level
-	sb_config->BuildParameters.EhciSsid				= EHCI_SSID;					// Board Level
-	sb_config->BuildParameters.Ohci4Ssid			= OHCI4_SSID;					// Board Level
-	sb_config->BuildParameters.SmbusSsid			= SMBUS_SSID;					// Board Level
-	sb_config->BuildParameters.IdeSsid				= IDE_SSID;						// Board Level
-	sb_config->BuildParameters.AzaliaSsid			= AZALIA_SSID;					// Board Level
-	sb_config->BuildParameters.LpcSsid				= LPC_SSID;						// Board Level
-	// sb_config->BuildParameters.PCIBSsid				= PCIB_SSID;					// Field Retired
-
-	//
-	// Common Function
-	//
-	sb_config->SATAMODE.SataMode.SataController		= SATA_CONTROLLER;				// External Option
-	sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt	= SATA_IDE_COMBMD_PRISEC_OPT;	// External Option
-	sb_config->SATAMODE.SataMode.SataIdeCombinedMode	= SATA_IDECOMBINED_MODE;	// External Option
-	sb_config->S3Resume								= 0;							// CIMx Internal Used
-	sb_config->SpreadSpectrum						= INCHIP_SPREAD_SPECTRUM;		// Board Level
-	sb_config->NbSbGen2								= INCHIP_NB_SB_GEN2;			// External Option
-	sb_config->GppGen2								= INCHIP_GPP_GEN2;				// External Option
-	sb_config->GppMemWrImprove						= INCHIP_GPP_MEMORY_WRITE_IMPROVE;	// Internal Option
-	sb_config->S4Resume								= 0;							// CIMx Internal Used
-	sb_config->SataClass							= CONFIG_SATA_CONTROLLER_MODE;	// INCHIP_SATA_MODE	// External Option
-	sb_config->SataIdeMode							= INCHIP_IDE_MODE;				// External Option
-	sb_config->sdConfig								= SB_SD_CONFIG;					// External Option
-	sb_config->sdSpeed								= SB_SD_SPEED;					// Internal Option
-	sb_config->sdBitwidth							= SB_SD_BITWIDTH;				// Internal Option
-	sb_config->SataDisUnusedIdePChannel				= SATA_DISUNUSED_IDE_P_CHANNEL;	// External Option
-	sb_config->SataDisUnusedIdeSChannel				= SATA_DISUNUSED_IDE_S_CHANNEL;	// External Option
-	sb_config->IdeDisUnusedIdePChannel				= IDE_DISUNUSED_IDE_P_CHANNEL;	// External Option
-	sb_config->IdeDisUnusedIdeSChannel				= IDE_DISUNUSED_IDE_S_CHANNEL;	// External Option
-	sb_config->SATAESPPORT.SataEspPort.PORT0		= SATA_ESP_PORT0;				// Board Level
-	sb_config->SATAESPPORT.SataEspPort.PORT1		= SATA_ESP_PORT1;				// Board Level
-	sb_config->SATAESPPORT.SataEspPort.PORT2		= SATA_ESP_PORT2;				// Board Level
-	sb_config->SATAESPPORT.SataEspPort.PORT3		= SATA_ESP_PORT3;				// Board Level
-	sb_config->SATAESPPORT.SataEspPort.PORT4		= SATA_ESP_PORT4;				// Board Level
-	sb_config->SATAESPPORT.SataEspPort.PORT5		= SATA_ESP_PORT5;				// Board Level
-	sb_config->SATAESPPORT.SataEspPort.PORT6		= SATA_ESP_PORT6;				// Board Level
-	sb_config->SATAESPPORT.SataEspPort.PORT7		= SATA_ESP_PORT7;				// Board Level
-	sb_config->SATAPORTPOWER.SataPortPower.PORT0	= SATA_PORT_POWER_PORT0;		// Board Level
-	sb_config->SATAPORTPOWER.SataPortPower.PORT1	= SATA_PORT_POWER_PORT1;		// Board Level
-	sb_config->SATAPORTPOWER.SataPortPower.PORT2	= SATA_PORT_POWER_PORT2;		// Board Level
-	sb_config->SATAPORTPOWER.SataPortPower.PORT3	= SATA_PORT_POWER_PORT3;		// Board Level
-	sb_config->SATAPORTPOWER.SataPortPower.PORT4	= SATA_PORT_POWER_PORT4;		// Board Level
-	sb_config->SATAPORTPOWER.SataPortPower.PORT5	= SATA_PORT_POWER_PORT5;		// Board Level
-	sb_config->SATAPORTPOWER.SataPortPower.PORT6	= SATA_PORT_POWER_PORT6;		// Board Level
-	sb_config->SATAPORTPOWER.SataPortPower.PORT7	= SATA_PORT_POWER_PORT7;		// Board Level
-	sb_config->SATAPORTMODE.SataPortMd.PORT0		= SATA_PORTMODE_PORT0;			// Board Level
-	sb_config->SATAPORTMODE.SataPortMd.PORT1		= SATA_PORTMODE_PORT1;			// Board Level
-	sb_config->SATAPORTMODE.SataPortMd.PORT2		= SATA_PORTMODE_PORT2;			// Board Level
-	sb_config->SATAPORTMODE.SataPortMd.PORT3		= SATA_PORTMODE_PORT3;			// Board Level
-	sb_config->SATAPORTMODE.SataPortMd.PORT4		= SATA_PORTMODE_PORT4;			// Board Level
-	sb_config->SATAPORTMODE.SataPortMd.PORT5		= SATA_PORTMODE_PORT5;			// Board Level
-	sb_config->SATAPORTMODE.SataPortMd.PORT6		= SATA_PORTMODE_PORT6;			// Board Level
-	sb_config->SATAPORTMODE.SataPortMd.PORT7		= SATA_PORTMODE_PORT7;			// Board Level
-	sb_config->SataAggrLinkPmCap					= INCHIP_SATA_AGGR_LINK_PM_CAP;	// Internal Option
-	sb_config->SataPortMultCap						= INCHIP_SATA_PORT_MULT_CAP;	// Internal Option
-	sb_config->SataClkAutoOff						= INCHIP_SATA_CLK_AUTO_OFF;		// External Option
-	sb_config->SataPscCap							= INCHIP_SATA_PSC_CAP;			// External Option
-	sb_config->SataFisBasedSwitching				= INCHIP_SATA_FIS_BASE_SW;		// External Option
-	sb_config->SataCccSupport						= INCHIP_SATA_CCC_SUPPORT;		// External Option
-	sb_config->SataSscCap							= INCHIP_SATA_SSC_CAP;			// External Option
-	sb_config->SataMsiCapability					= INCHIP_SATA_MSI_CAP;			// Internal Option
-	sb_config->SataForceRaid						= INCHIP_SATA_FORCE_RAID5;		// Internal Option
-	sb_config->SataTargetSupport8Device				= CIMXSB_SATA_TARGET_8DEVICE_CAP;	// External Option
-	sb_config->SataDisableGenericMode				= SATA_DISABLE_GENERIC_MODE_CAP;// External Option
-	sb_config->SataAhciEnclosureManagement			= SATA_AHCI_ENCLOSURE_CAP;		// Internal Option
-	sb_config->SataSgpio0							= SATA_GPIO_0_CAP;				// External Option
-	sb_config->SataSgpio1							= SATA_GPIO_1_CAP;				// External Option
-	sb_config->SataPhyPllShutDown					= SATA_PHY_PLL_SHUTDOWN;		// External Option
-	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT0	= SATA_HOTREMOVEL_ENH_PORT0;	// Board Level
-	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT1	= SATA_HOTREMOVEL_ENH_PORT1;	// Board Level
-	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT2	= SATA_HOTREMOVEL_ENH_PORT2;	// Board Level
-	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT3	= SATA_HOTREMOVEL_ENH_PORT3;	// Board Level
-	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT4	= SATA_HOTREMOVEL_ENH_PORT4;	// Board Level
-	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT5	= SATA_HOTREMOVEL_ENH_PORT5;	// Board Level
-	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT6	= SATA_HOTREMOVEL_ENH_PORT6;	// Board Level
-	sb_config->SATAHOTREMOVALENH.SataHotRemoveEnhPort.PORT7	= SATA_HOTREMOVEL_ENH_PORT7;	// Board Level
-	// USB
-	sb_config->USBMODE.UsbMode.Ohci1				= INCHIP_USB_OHCI1_CINFIG;		// External Option
-	sb_config->USBMODE.UsbMode.Ehci1				= INCHIP_USB_EHCI1_CINFIG;		// Internal Option*
-	sb_config->USBMODE.UsbMode.Ohci2				= INCHIP_USB_OHCI2_CINFIG;		// External Option
-	sb_config->USBMODE.UsbMode.Ehci2				= INCHIP_USB_EHCI2_CINFIG;		// Internal Option*
-	sb_config->USBMODE.UsbMode.Ohci3				= INCHIP_USB_OHCI3_CINFIG;		// External Option
-	sb_config->USBMODE.UsbMode.Ehci3				= INCHIP_USB_EHCI3_CINFIG;		// Internal Option*
-	sb_config->USBMODE.UsbMode.Ohci4				= INCHIP_USB_OHCI4_CINFIG;		// External Option
-	// GEC
-	sb_config->GecConfig							= INCHIP_GEC_CONTROLLER;		// External Option
-	sb_config->IrConfig								= SB_IR_CONTROLLER;				// External Option
-	sb_config->XhciSwitch							= SB_XHCI_SWITCH;				// External Option
-	// Azalia
-	sb_config->AzaliaController						= INCHIP_AZALIA_CONTROLLER;		// External Option
-	sb_config->AzaliaPinCfg							= INCHIP_AZALIA_PIN_CONFIG;		// Board Level
-	sb_config->FrontPanelDetected					= INCHIP_FRONT_PANEL_DETECTED;	// Board Level
-	sb_config->AZALIACONFIG.AzaliaSdinPin			= AZALIA_PIN_CONFIG;			// Board Level
-	sb_config->AZOEMTBL.pAzaliaOemCodecTablePtr		= NULL;							// Board Level
-	sb_config->AZOEMFPTBL.pAzaliaOemFpCodecTablePtr	= NULL;							// Board Level
-	sb_config->AnyHT200MhzLink						= INCHIP_ANY_HT_200MHZ_LINK;	// Internal Option
-	sb_config->HpetTimer							= SB_HPET_TIMER;				// External Option
-	sb_config->AzaliaSnoop							= INCHIP_AZALIA_SNOOP;			// Internal Option*
-	// Generic
-	sb_config->NativePcieSupport					= INCHIP_NATIVE_PCIE_SUPPOORT;	// External Option
-	// USB
-	sb_config->UsbPhyPowerDown						= INCHIP_USB_PHY_POWER_DOWN;	// External Option
-	sb_config->PcibClkStopOverride					= INCHIP_PCIB_CLK_STOP_OVERRIDE;// Internal Option
-	// sb_config->HpetMsiDis							= 0;								// Field Retired
-	// sb_config->ResetCpuOnSyncFlood					= 0;								// Field Retired
-	// sb_config->PcibAutoClkCtr						= 0;								// Field Retired
-	sb_config->OEMPROGTBL.OemProgrammingTablePtr	= (uintptr_t)NULL;							// Board Level
-	sb_config->PORTCONFIG[0].PortCfg.PortPresent	= SB_GPP_PORT0;					// Board Level
-	sb_config->PORTCONFIG[0].PortCfg.PortDetected	= 0;							// CIMx Internal Used
-	sb_config->PORTCONFIG[0].PortCfg.PortIsGen2		= 0;							// CIMx Internal Used
-	sb_config->PORTCONFIG[0].PortCfg.PortHotPlug	= 0;							// CIMx Internal Used
-	// sb_config->PORTCONFIG[0].PortCfg.PortIntxMap		= 0;								// Field Retired
-	sb_config->PORTCONFIG[1].PortCfg.PortPresent	= SB_GPP_PORT1;					// Board Level
-	sb_config->PORTCONFIG[1].PortCfg.PortDetected	= 0;							// CIMx Internal Used
-	sb_config->PORTCONFIG[1].PortCfg.PortIsGen2		= 0;							// CIMx Internal Used
-	sb_config->PORTCONFIG[1].PortCfg.PortHotPlug	= 0;							// CIMx Internal Used
-	// sb_config->PORTCONFIG[0].PortCfg.PortIntxMap		= 0;								// Field Retired
-	sb_config->PORTCONFIG[2].PortCfg.PortPresent	= SB_GPP_PORT2;					// Board Level
-	sb_config->PORTCONFIG[2].PortCfg.PortDetected	= 0;							// CIMx Internal Used
-	sb_config->PORTCONFIG[2].PortCfg.PortIsGen2		= 0;							// CIMx Internal Used
-	sb_config->PORTCONFIG[2].PortCfg.PortHotPlug	= 0;							// CIMx Internal Used
-	// sb_config->PORTCONFIG[0].PortCfg.PortIntxMap		= 0;								// Field Retired
-	sb_config->PORTCONFIG[3].PortCfg.PortPresent	= SB_GPP_PORT3;					// Board Level
-	sb_config->PORTCONFIG[3].PortCfg.PortDetected	= 0;							// CIMx Internal Used
-	sb_config->PORTCONFIG[3].PortCfg.PortIsGen2		= 0;							// CIMx Internal Used
-	sb_config->PORTCONFIG[3].PortCfg.PortHotPlug	= 0;							// CIMx Internal Used
-	// sb_config->PORTCONFIG[0].PortCfg.PortIntxMap		= 0;								// Field Retired
-	sb_config->GppLinkConfig						= INCHIP_GPP_LINK_CONFIG;		// External Option
-	sb_config->GppFoundGfxDev						= 0;							// CIMx Internal Used
-	sb_config->GppFunctionEnable					= SB_GPP_CONTROLLER;			// External Option
-	sb_config->GppUnhidePorts						= INCHIP_GPP_UNHIDE_PORTS;		// Internal Option
-	sb_config->GppPortAspm							= INCHIP_GPP_PORT_ASPM;			// Internal Option
-	sb_config->GppLaneReversal						= INCHIP_GPP_LANEREVERSAL;		// External Option
-	sb_config->AlinkPhyPllPowerDown					= INCHIP_ALINK_PHY_PLL_POWER_DOWN;	// External Option
-	sb_config->GppPhyPllPowerDown					= INCHIP_GPP_PHY_PLL_POWER_DOWN;// External Option
-	sb_config->GppDynamicPowerSaving				= INCHIP_GPP_DYNAMIC_POWER_SAVING;	// External Option
-	sb_config->PcieAER								= INCHIP_PCIE_AER;				// External Option
-	sb_config->PcieRAS								= INCHIP_PCIE_RAS;				// External Option
-	sb_config->GppHardwareDowngrade					= INCHIP_GPP_HARDWARE_DOWNGRADE;// Internal Option
-	sb_config->GppToggleReset						= INCHIP_GPP_TOGGLE_RESET;		// External Option
-	sb_config->sdbEnable							= 0;							// CIMx Internal Used
-	sb_config->TempMMIO								= (UINTN)NULL;							// CIMx Internal Used
-	// sb_config->GecPhyStatus							= INCHIP_GEC_PHY_STATUS;		// Field Retired
-	sb_config->SBGecPwr								= INCHIP_GEC_POWER_POLICY;		// Internal Option
-	sb_config->SBGecDebugBus						= INCHIP_GEC_DEBUGBUS;			// Internal Option
-	sb_config->SbPcieOrderRule						= INCHIP_SB_PCIE_ORDER_RULE;	// External Option
-	sb_config->AcDcMsg								= INCHIP_ACDC_MSG;				// Internal Option
-	sb_config->TimerTickTrack						= INCHIP_TIMER_TICK_TRACK;		// Internal Option
-	sb_config->ClockInterruptTag					= INCHIP_CLOCK_INTERRUPT_TAG;	// Internal Option
-	sb_config->OhciTrafficHanding					= INCHIP_OHCI_TRAFFIC_HANDING;	// Internal Option
-	sb_config->EhciTrafficHanding					= INCHIP_EHCI_TRAFFIC_HANDING;	// Internal Option
-	sb_config->FusionMsgCMultiCore					= INCHIP_FUSION_MSGC_MULTICORE;	// Internal Option
-	sb_config->FusionMsgCStage						= INCHIP_FUSION_MSGC_STAGE;		// Internal Option
-	sb_config->ALinkClkGateOff						= INCHIP_ALINK_CLK_GATE_OFF;	// External Option
-	sb_config->BLinkClkGateOff						= INCHIP_BLINK_CLK_GATE_OFF;	// External Option
-	// sb_config->sdb									= 0;								// Field Retired
-	sb_config->GppGen2Strap							= 0;							// CIMx Internal Used
-	sb_config->SlowSpeedABlinkClock					= INCHIP_SLOW_SPEED_ABLINK_CLOCK;	// Internal Option
-	sb_config->DYNAMICGECROM.DynamicGecRomAddress_Ptr	= NULL;						// Board Level
-	sb_config->AbClockGating						= INCHIP_AB_CLOCK_GATING;		// External Option
-	sb_config->GppClockGating						= INCHIP_GPP_CLOCK_GATING;		// External Option
-	sb_config->L1TimerOverwrite						= INCHIP_L1_TIMER_OVERWRITE;	// Internal Option
-	// sb_config->UmiLinkWidth							= 0;								// Field Retired
-	sb_config->UmiDynamicSpeedChange				= INCHIP_UMI_DYNAMIC_SPEED_CHANGE;	// Internal Option
-	// sb_config->PcieRefClockOverclocking				= 0;								// Field Retired
-	sb_config->SbAlinkGppTxDriverStrength			= INCHIP_ALINK_GPP_TX_DRV_STRENGTH;	// Internal Option
-	sb_config->PwrFailShadow						= 0x02;							// Board Level
-	sb_config->StressResetMode						= INCHIP_STRESS_RESET_MODE;		// Internal Option
-	sb_config->hwm.fanSampleFreqDiv					= 0x03;							// Board Level
-	sb_config->hwm.hwmSbtsiAutoPoll					= 1;							// Board Level
-
-	/* General */
-	sb_config->PciClks								= SB_PCI_CLOCK_RESERVED;
-	sb_config->hwm.hwmEnable						= 0x0;
-
-	/* ramstage cimx config here */
-	if (ENV_RAMSTAGE && !sb_config->StdHeader.CALLBACK.CalloutPtr) {
-		sb_config->StdHeader.CALLBACK.CalloutPtr = sb900_callout_entry;
-	}
-
-	//sb_config->
-	printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - End.\n");
-}
-
-void SbPowerOnInit_Config(AMDSBCFG *sb_config)
-{
-	if (!sb_config) {
-	printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
-		return;
-	}
-    printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");
-	memset(sb_config, 0, sizeof(AMDSBCFG));
-
-    // Set the build parameters
-	sb_config->BuildParameters.BiosSize				= BIOS_SIZE;					// Field Retired
-	sb_config->BuildParameters.LegacyFree			= SBCIMx_LEGACY_FREE;			// Board Level
-	sb_config->BuildParameters.SpiSpeed				= SBCIMX_SPI_SPEED;				// Internal Option
-	sb_config->BuildParameters.SpiFastSpeed			= SBCIMX_SPI_FASTSPEED;			// Internal Option
-	// sb_config->BuildParameters.SpiWriteSpeed			=  0;							// Field Retired
-	sb_config->BuildParameters.SpiMode				= SBCIMX_SPI_MODE;				// Internal Option
-	sb_config->BuildParameters.SpiBurstWrite		= SBCIMX_SPI_BURST_WRITE;		// Internal Option
-	sb_config->BuildParameters.EcKbd				= INCHIP_EC_KBD;				// Board Level
-	sb_config->BuildParameters.Smbus0BaseAddress	= SMBUS0_BASE_ADDRESS;			// Board Level
-	sb_config->BuildParameters.Smbus1BaseAddress	= SMBUS1_BASE_ADDRESS;			// Board Level
-	sb_config->BuildParameters.SioPmeBaseAddress	= SIO_PME_BASE_ADDRESS;			// Board Level
-	sb_config->BuildParameters.WatchDogTimerBase	= WATCHDOG_TIMER_BASE_ADDRESS;	// Board Level
-	sb_config->BuildParameters.GecShadowRomBase		= GEC_ROM_SHADOW_ADDRESS;		// Board Level
-	sb_config->BuildParameters.SpiRomBaseAddress	= SPI_BASE_ADDRESS;				// Board Level
-	sb_config->BuildParameters.AcpiPm1EvtBlkAddr	= PM1_EVT_BLK_ADDRESS;			// Board Level
-	sb_config->BuildParameters.AcpiPm1CntBlkAddr	= PM1_CNT_BLK_ADDRESS;			// Board Level
-	sb_config->BuildParameters.AcpiPmTmrBlkAddr		= PM1_TMR_BLK_ADDRESS;			// Board Level
-	sb_config->BuildParameters.CpuControlBlkAddr	= CPU_CNT_BLK_ADDRESS;			// Board Level
-	sb_config->BuildParameters.AcpiGpe0BlkAddr		= GPE0_BLK_ADDRESS;				// Board Level
-	sb_config->BuildParameters.SmiCmdPortAddr		= SMI_CMD_PORT;					// Board Level
-	sb_config->BuildParameters.AcpiPmaCntBlkAddr	= ACPI_PMA_CNT_BLK_ADDRESS;		// Board Level
-    sb_config->SATAMODE.SataMode.SataController		= INCHIP_SATA_CONTROLLER;		// External Option
-    sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt	= SATA_COMBINE_MODE_CHANNEL;// External Option
-    sb_config->SATAMODE.SataMode.SataSetMaxGen2		= SATA_MAX_GEN2_MODE;			// External Option
-    sb_config->SATAMODE.SataMode.SataIdeCombinedMode= SATA_COMBINE_MODE;			// External Option
-    sb_config->SATAMODE.SataMode.SataClkMode		= SATA_CLK_RESERVED;			// Internal Option
-    sb_config->NbSbGen2								= NB_SB_GEN2;					// External Option
-    sb_config->SataInternal100Spread				= INCHIP_SATA_INTERNAL_100_SPREAD;	// External Option
-    sb_config->OEMPROGTBL.OemProgrammingTablePtr	= (uintptr_t)NULL;							// Board Level
-    sb_config->sdbEnable							= 0;							// CIMx Internal Used
-    sb_config->Cg2Pll								= INCHIP_CG2_PLL;				// Internal Option
-
-    printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - End.\n");
-}
--- a/src/southbridge/amd/cimx/sb900/chip.h
+++ b/src/southbridge/amd/cimx/sb900/chip.h
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _CIMX_SB900_CHIP_H_
-#define _CIMX_SB900_CHIP_H_
-
-/*
- * configuration set in mainboard/devicetree.cb
- *  boot_switch_sata_ide:
- *   0 -set SATA as primary, PATA(IDE) as secondary.
- *   1 -set PATA(IDE) as primary, SATA as secondary. if you want to boot from IDE,
- *  gpp_configuration - The configuration of General Purpose Port A/B/C/D
- *   0(GPP_CFGMODE_X4000) -PortA Lanes[3:0]
- *   2(GPP_CFGMODE_X2200) -PortA Lanes[1:0], PortB Lanes[3:2]
- *   3(GPP_CFGMODE_X2110) -PortA Lanes[1:0], PortB Lane2, PortC Lane3
- *   4(GPP_CFGMODE_X1111) -PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
- */
-struct southbridge_amd_cimx_sb900_config
-{
-	u32 boot_switch_sata_ide : 1;
-	u8  gpp_configuration;
-};
-
-#endif /* _CIMX_SB900_CHIP_H_ */
--- a/src/southbridge/amd/cimx/sb900/early.c
+++ b/src/southbridge/amd/cimx/sb900/early.c
@@ -1,138 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <stdint.h>
-#include <arch/io.h>
-#include "SbPlatform.h"
-#include "sb_cimx.h"
-#include <console/console.h>
-#include "smbus.h"
-
-
-/**
- * @brief South Bridge CIMx romstage entry,
- *        wrapper of sbPowerOnInit entry point.
- */
-void sb_poweron_init(void)
-{
-	AMDSBCFG sb_early_cfg;
-	u8 data;
-
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - Start.\n");
-
-	//Enable/Disable PCI Bridge Device 14 Function 4.
-	outb(0xEA, 0xCD6);
-	data = inb(0xCD7);
-	data &= ~BIT0;
-	if (!CONFIG(PCIB_ENABLE)) {
-		data |= BIT0;
-	}
-	outb(data, 0xCD7);
-
-	SbPowerOnInit_Config(&sb_early_cfg);
-	//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
-	//AmdSbDispatcher(&sb_early_cfg);
-	//TODO
-	//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
-	// VerifyImage() will fail, LocateImage() takes minutes to find the image.
-	sbPowerOnInit(&sb_early_cfg);
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_poweron_init - End.\n");
-}
-
-/**
- * @brief South Bridge CIMx romstage entry,
- *        wrapper of sbPowerOnInit entry point.
- */
-void sb_before_pci_init(void)
-{
-	AMDSBCFG sb_early_cfg;
-
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - Start.\n");
-	sb900_cimx_config(&sb_early_cfg);
-	//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
-	//AmdSbDispatcher(&sb_early_cfg);
-	//TODO
-	//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
-	// VerifyImage() will fail, LocateImage() takes minutes to find the image.
-	sbBeforePciInit(&sb_early_cfg);
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_before_pci_init - End.\n");
-}
-
-void sb_After_Pci_Init(void)
-{
-	AMDSBCFG sb_early_cfg;
-
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n");
-	sb900_cimx_config(&sb_early_cfg);
-	//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
-	//AmdSbDispatcher(&sb_early_cfg);
-	//TODO
-	//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
-	// VerifyImage() will fail, LocateImage() takes minutes to find the image.
-	sbAfterPciInit(&sb_early_cfg);
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n");
-}
-
-void sb_Mid_Post_Init(void)
-{
-	AMDSBCFG sb_early_cfg;
-
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - Start.\n");
-	sb900_cimx_config(&sb_early_cfg);
-	//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
-	//AmdSbDispatcher(&sb_early_cfg);
-	//TODO
-	//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
-	// VerifyImage() will fail, LocateImage() takes minutes to find the image.
-	sbMidPostInit(&sb_early_cfg);
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_Mid_Post_Init - End.\n");
-}
-
-void sb_Late_Post(void)
-{
-	AMDSBCFG sb_early_cfg;
-	u8 data;
-
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - Start.\n");
-	sb900_cimx_config(&sb_early_cfg);
-	//sb_early_cfg.StdHeader.Func = SB_POWERON_INIT;
-	//AmdSbDispatcher(&sb_early_cfg);
-	//TODO
-	//AMD_IMAGE_HEADER was missing, when using AmdSbDispatcher,
-	// VerifyImage() will fail, LocateImage() takes minutes to find the image.
-	sbLatePost(&sb_early_cfg);
-
-	//Set ACPI SCI IRQ to 0x9.
-	data = CONFIG_ACPI_SCI_IRQ;
-	outb(0x10, 0xC00);
-	outb(data, 0xC01);
-	outb(0x90, 0xC00);
-	outb(data, 0xC01);
-
-	if (data > 0x7) {
-		data = inb(0x4D1);
-		data |= (1 << (CONFIG_ACPI_SCI_IRQ - 8));
-		outb(data, 0x4D1);
-	} else {
-		data = inb(0x4D0);
-		data |= (1 << (CONFIG_ACPI_SCI_IRQ));
-		outb(data, 0x4D0);
-	}
-
-	printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - End.\n");
-}
--- a/src/southbridge/amd/cimx/sb900/gpio_oem.h
+++ b/src/southbridge/amd/cimx/sb900/gpio_oem.h
@@ -1,66 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _GPIO_OEM_H_
-#define _GPIO_OEM_H_
-
-/* Hudson-2 ACPI PmIO Space Define */
-#define SB_ACPI_BASE_ADDRESS              0x0400
-#define VACPI_MMIO_BASE  ((u8 *)0xFED80000)
-#define SB_CFG_BASE     0x000   // DWORD
-#define GPIO_BASE       0x100   // BYTE
-#define SMI_BASE        0x200   // DWORD
-#define PMIO_BASE       0x300   // DWORD
-#define PMIO2_BASE      0x400   // BYTE
-#define BIOS_RAM_BASE   0x500   // BYTE
-#define CMOS_RAM_BASE   0x600   // BYTE
-#define CMOS_BASE       0x700   // BYTE
-#define ASF_BASE        0x900   // DWORD
-#define SMBUS_BASE      0xA00   // DWORD
-#define WATCHDOG_BASE   0xB00   // ??
-#define HPET_BASE       0xC00   // DWORD
-#define IOMUX_BASE      0xD00   // BYTE
-#define MISC_BASE       0xE00
-#define SERIAL_DEBUG_BASE  0x1000
-#define GFX_DAC_BASE       0x1400
-#define CEC_BASE           0x1800
-#define XHCI_BASE          0x1C00
-#define ACPI_SMI_DATA_PORT                0xB1
-#define R_SB_ACPI_PM1_STATUS              0x00
-#define R_SB_ACPI_PM1_ENABLE              0x02
-#define R_SB_ACPI_PM_CONTROL              0x04
-#define R_SB_ACPI_EVENT_STATUS            0x20
-#define R_SB_ACPI_EVENT_ENABLE            0x24
-#define   B_PWR_BTN_STATUS                BIT8
-#define   B_WAKEUP_STATUS                 BIT15
-#define   B_SCI_EN                        BIT0
-#define SB_PM_INDEX_PORT                  0xCD6
-#define SB_PM_DATA_PORT                   0xCD7
-#define SB_PMIOA_REG24          0x24        //  AcpiMmioEn
-#define MmioAddress( BaseAddr, Register ) \
-  ( (UINTN)BaseAddr + \
-    (UINTN)(Register) \
-  )
-#define Mmio32Ptr( BaseAddr, Register ) \
-  ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
-#define Mmio32( BaseAddr, Register ) \
-  *Mmio32Ptr( BaseAddr, Register )
-
-#define SB_GPIO_REG01   1
-#define SB_GPIO_REG02   2
-#define SB_GPIO_REG15   15
-#define SB_GPIO_REG24   24
-#define SB_GPIO_REG25   25
-#define SB_GPIO_REG27   27
-
-#endif
--- a/src/southbridge/amd/cimx/sb900/late.c
+++ b/src/southbridge/amd/cimx/sb900/late.c
@@ -1,457 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <device/device.h>
-#include <device/pci.h>		/* device_operations */
-#include <device/pci_ids.h>
-#include <device/smbus.h>	/* smbus_bus_operations */
-#include <pc80/mc146818rtc.h>
-#include <pc80/i8254.h>
-#include <pc80/i8259.h>
-#include <console/console.h>	/* printk */
-#include <device/pci_ehci.h>
-#include <arch/acpi.h>
-#include "lpc.h"		/* lpc_read_resources */
-#include "SbPlatform.h"		/* Platform Specific Definitions */
-#include "chip.h"		/* struct southbridge_amd_cimx_sb900_config */
-
-#ifndef _RAMSTAGE_
-#define _RAMSTAGE_
-#endif
-static AMDSBCFG sb_late_cfg; //global, init in sb900_cimx_config
-static AMDSBCFG *sb_config = &sb_late_cfg;
-
-
-/**
- * @brief Entry point of Southbridge CIMx callout
- *
- * prototype UINT32 (*SBCIM_HOOK_ENTRY)(UINT32 Param1, UINT32 Param2, void* pConfig)
- *
- * @param[in] func      Southbridge CIMx Function ID.
- * @param[in] data      Southbridge Input Data.
- * @param[in] config    Southbridge configuration structure pointer.
- *
- */
-u32 sb900_callout_entry(u32 func, u32 data, void *config)
-{
-	u32 ret = 0;
-
-	printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - Start.\n");
-	switch (func) {
-	case CB_SBGPP_RESET_ASSERT:
-		break;
-
-	case CB_SBGPP_RESET_DEASSERT:
-		break;
-
-//-	case IMC_FIRMWARE_FAIL:
-//-		break;
-
-	default:
-		break;
-	}
-
-	printk(BIOS_DEBUG, "SB900 - Late.c - sb900_callout_entry - End.\n");
-	return ret;
-}
-
-
-static struct pci_operations lops_pci = {
-	.set_subsystem = 0,
-};
-
-static void lpc_enable_resources(struct device *dev)
-{
-
-	printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - Start.\n");
-	pci_dev_enable_resources(dev);
-	//lpc_enable_childrens_resources(dev);
-	printk(BIOS_DEBUG, "SB900 - Late.c - lpc_enable_resources - End.\n");
-}
-
-static void lpc_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - Start.\n");
-	/* SB Configure HPET base and enable bit */
-//-	hpetInit(sb_config, &(sb_config->BuildParameters));
-	cmos_check_update_date();
-
-	/* Initialize the real time clock.
-	 * The 0 argument tells cmos_init not to
-	 * update CMOS unless it is invalid.
-	 * 1 tells cmos_init to always initialize the CMOS.
-	 */
-	cmos_init(0);
-
-	setup_i8259(); /* Initialize i8259 pic */
-	setup_i8254(); /* Initialize i8254 timers */
-
-	printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n");
-}
-
-unsigned long acpi_fill_mcfg(unsigned long current)
-{
-	/* Just a dummy */
-	return current;
-}
-
-static struct device_operations lpc_ops = {
-	.read_resources = lpc_read_resources,
-	.set_resources = lpc_set_resources,
-	.enable_resources = lpc_enable_resources,
-	.init = lpc_init,
-#if CONFIG(HAVE_ACPI_TABLES)
-	.write_acpi_tables = acpi_write_hpet,
-#endif
-	.scan_bus = scan_static_bus,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
-	.ops = &lpc_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_LPC,
-};
-
-
-static void sata_enable_resources(struct device *dev)
-{
-	printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - Start.\n");
-//-	sataInitAfterPciEnum(sb_config);
-	pci_dev_enable_resources(dev);
-	printk(BIOS_DEBUG, "SB900 - Late.c - sata_enable_resources - End.\n");
-}
-
-static void sata_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - Start.\n");
-	sb_config->StdHeader.Func = SB_MID_POST_INIT;
-//-	AmdSbDispatcher(sb_config); //sataInitMidPost only
-//-	commonInitLateBoot(sb_config);
-//-	sataInitLatePost(sb_config);
-	printk(BIOS_DEBUG, "SB900 - Late.c - sata_init - End.\n");
-}
-
-static struct device_operations sata_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = sata_enable_resources, //pci_dev_enable_resources,
-	.init = sata_init,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver sata_driver __pci_driver = {
-	.ops = &sata_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-#if (CONFIG_SATA_CONTROLLER_MODE == 0x0 || CONFIG_SATA_CONTROLLER_MODE == 0x3)
-	.device = PCI_DEVICE_ID_AMD_SB900_SATA,	//SATA IDE Mode
-#endif
-#if (CONFIG_SATA_CONTROLLER_MODE == 0x2 || CONFIG_SATA_CONTROLLER_MODE == 0x4)
-	.device = PCI_DEVICE_ID_AMD_SB900_SATA_AHCI,	//SATA AHCI Mode
-#endif
-#if (CONFIG_SATA_CONTROLLER_MODE == 0x5 || CONFIG_SATA_CONTROLLER_MODE == 0x6)
-	.device = PCI_DEVICE_ID_AMD_SB900_SATA_AMDAHCI,	//SATA AMDAHCI Mode
-#endif
-#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x0)
-	.device = PCI_DEVICE_ID_AMD_SB900_SATA_RAID5,	//SATA RAID5 Mode
-#endif
-#if (CONFIG_SATA_CONTROLLER_MODE == 0x1 && INCHIP_SATA_FORCE_RAID5 == 0x1)
-	.device = PCI_DEVICE_ID_AMD_SB900_SATA_RAID,	//SATA RAID Mode
-#endif
-};
-
-static void usb_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - Start.\n");
-//-	usbInitAfterPciInit(sb_config);
-//-	commonInitLateBoot(sb_config);
-	printk(BIOS_DEBUG, "SB900 - Late.c - usb_init - End.\n");
-}
-
-static struct device_operations usb_ops = {
-	.read_resources = pci_ehci_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = usb_init,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-/*
- * The pci id of usb ctrl 0 and 1 are the same.
- */
-static const struct pci_driver usb_xhci123_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_USB_16_0, /* XHCI-USB1, XHCI-USB2 */
-};
-
-static const struct pci_driver usb_ohci123_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_USB_18_0, /* OHCI-USB1, OHCI-USB2, OHCI-USB3 */
-};
-
-static const struct pci_driver usb_ehci123_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_USB_18_2, /* EHCI-USB1, EHCI-USB2, EHCI-USB3 */
-};
-
-static const struct pci_driver usb_ohci4_driver __pci_driver = {
-	.ops = &usb_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_USB_20_5, /* OHCI-USB4 */
-};
-
-
-static void azalia_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - Start.\n");
-//-	azaliaInitAfterPciEnum(sb_config); //Detect and configure High Definition Audio
-	printk(BIOS_DEBUG, "SB900 - Late.c - azalia_init - End.\n");
-}
-
-static struct device_operations azalia_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = azalia_init,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver azalia_driver __pci_driver = {
-	.ops = &azalia_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_HDA,
-};
-
-
-static void gec_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - Start.\n");
-//-	gecInitAfterPciEnum(sb_config);
-//-	gecInitLatePost(sb_config);
-	printk(BIOS_DEBUG, "SB900 - Late.c - gec_init - End.\n");
-}
-
-static struct device_operations gec_ops = {
-	.read_resources = pci_dev_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_dev_enable_resources,
-	.init = gec_init,
-	.scan_bus = 0,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver gec_driver __pci_driver = {
-	.ops = &gec_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_GEC,
-};
-
-
-static void pcie_init(struct device *dev)
-{
-	printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - Start.\n");
-//-	sbPcieGppLateInit(sb_config);
-	printk(BIOS_DEBUG, "SB900 - Late.c - pcie_init - End.\n");
-}
-
-static struct device_operations pci_ops = {
-	.read_resources = pci_bus_read_resources,
-	.set_resources = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init = pcie_init,
-	.scan_bus = pci_scan_bridge,
-	.reset_bus = pci_bus_reset,
-	.ops_pci = &lops_pci,
-};
-
-static const struct pci_driver pci_driver __pci_driver = {
-	.ops = &pci_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCI,
-};
-
-
-struct device_operations bridge_ops = {
-	.read_resources   = pci_bus_read_resources,
-	.set_resources    = pci_dev_set_resources,
-	.enable_resources = pci_bus_enable_resources,
-	.init             = pcie_init,
-	.scan_bus         = pci_scan_bridge,
-	.enable           = 0,
-	.reset_bus        = pci_bus_reset,
-	.ops_pci          = &lops_pci,
-};
-
-/* 0:15:0 PCIe PortA */
-static const struct pci_driver PORTA_driver __pci_driver = {
-	.ops = &bridge_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCIEA,
-};
-
-/* 0:15:1 PCIe PortB */
-static const struct pci_driver PORTB_driver __pci_driver = {
-	.ops = &bridge_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCIEB,
-};
-
-/* 0:15:2 PCIe PortC */
-static const struct pci_driver PORTC_driver __pci_driver = {
-	.ops = &bridge_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCIEC,
-};
-
-/* 0:15:3 PCIe PortD */
-static const struct pci_driver PORTD_driver __pci_driver = {
-	.ops = &bridge_ops,
-	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_SB900_PCIED,
-};
-
-
-/**
- * @brief SB Cimx entry point sbBeforePciInit wrapper
- */
-static void sb900_enable(struct device *dev)
-{
-	u8 gpp_port = 0;
-	struct southbridge_amd_cimx_sb900_config *sb_chip =
-		(struct southbridge_amd_cimx_sb900_config *)(dev->chip_info);
-
-	sb900_cimx_config(sb_config);
-	printk(BIOS_DEBUG, "sb900_enable() ");
-
-	/* Config SouthBridge SMBUS/ACPI/IDE/LPC/PCIB.*/
-//-	commonInitEarlyBoot(sb_config);
-//-	commonInitEarlyPost(sb_config);
-
-	switch (dev->path.pci.devfn) {
-	case PCI_DEVFN(0x10, 0): /* XHCI-USB */
-//-		usbInitBeforePciEnum(sb_config);  // USB POST TIME Only
-		break;
-
-	case PCI_DEVFN(0x11, 0): /* SATA */
-		if (dev->enabled) {
-			sb_config->SATAMODE.SataMode.SataController = ENABLED;
-			if (sb_chip->boot_switch_sata_ide == 1)
-				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 0; //0 -IDE as primary.
-			else if (sb_chip->boot_switch_sata_ide == 0)
-				sb_config->SATAMODE.SataMode.SataIdeCombMdPriSecOpt = 1; //1 -IDE as secondary.
-		} else {
-			sb_config->SATAMODE.SataMode.SataController = DISABLED;
-		}
-
-//-		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
-		break;
-
-	case PCI_DEVFN(0x12, 0): /* OHCI-USB1 */
-	case PCI_DEVFN(0x12, 2): /* EHCI-USB1 */
-	case PCI_DEVFN(0x13, 0): /* OHCI-USB2 */
-	case PCI_DEVFN(0x13, 2): /* EHCI-USB2 */
-	case PCI_DEVFN(0x14, 5): /* OHCI-USB4 */
-//-		usbInitBeforePciEnum(sb_config);  // USB POST TIME Only
-		break;
-
-	case PCI_DEVFN(0x14, 0): /* SMBUS */
-		break;
-
-	case PCI_DEVFN(0x14, 1): /* IDE */
-		if (dev->enabled) {
-			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = ENABLED;
-		} else {
-			sb_config->SATAMODE.SataMode.SataIdeCombinedMode = DISABLED;
-		}
-//-		sataInitBeforePciEnum(sb_config); // Init SATA class code and PHY
-		break;
-
-	case PCI_DEVFN(0x14, 2): /* HDA */
-		if (dev->enabled) {
-			if (sb_config->AzaliaController == AZALIA_DISABLE) {
-				sb_config->AzaliaController = AZALIA_AUTO;
-			}
-			printk(BIOS_DEBUG, "hda enabled\n");
-		} else {
-			sb_config->AzaliaController = AZALIA_DISABLE;
-			printk(BIOS_DEBUG, "hda disabled\n");
-		}
-//-		azaliaInitBeforePciEnum(sb_config); // Detect and configure High Definition Audio
-		break;
-
-
-	case PCI_DEVFN(0x14, 3): /* LPC */
-		break;
-
-	case PCI_DEVFN(0x14, 4): /* PCI */
-		break;
-
-	case PCI_DEVFN(0x14, 6): /* GEC */
-		if (dev->enabled) {
-			sb_config->GecConfig = 0;
-			printk(BIOS_DEBUG, "gec enabled\n");
-		} else {
-			sb_config->GecConfig = 1;
-			printk(BIOS_DEBUG, "gec disabled\n");
-		}
-//-		gecInitBeforePciEnum(sb_config); // Init GEC
-		break;
-
-	case PCI_DEVFN(0x15, 0): /* PCIe PortA */
-	case PCI_DEVFN(0x15, 1): /* PCIe PortB */
-	case PCI_DEVFN(0x15, 2): /* PCIe PortC */
-	case PCI_DEVFN(0x15, 3): /* PCIe PortD */
-		gpp_port = (dev->path.pci.devfn) & 0x03;
-		if (dev->enabled) {
-			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = ENABLED;
-		} else {
-			sb_config->PORTCONFIG[gpp_port].PortCfg.PortPresent = DISABLED;
-		}
-
-		/*
-		 * GPP_CFGMODE_X4000: PortA Lanes[3:0]
-		 * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2]
-		 * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3
-		 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3
-		 */
-		if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) {
-			sb_config->GppLinkConfig = sb_chip->gpp_configuration;
-		}
-
-//-		sbPcieGppEarlyInit(sb_config);
-		break;
-
-	default:
-		break;
-	}
-
-	/* Special setting ABCFG registers before PCI emulation. */
-//-	abSpecialSetBeforePciEnum(sb_config);
-//-	usbDesertPll(sb_config);
-	//sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT;
-	//AmdSbDispatcher(sb_config);
-}
-
-struct chip_operations southbridge_amd_cimx_sb900_ops = {
-	CHIP_NAME("ATI SB900")
-	.enable_dev = sb900_enable,
-};
--- a/src/southbridge/amd/cimx/sb900/lpc.c
+++ b/src/southbridge/amd/cimx/sb900/lpc.c
@@ -1,182 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include "lpc.h"
-#include <console/console.h>	/* printk */
-#include <arch/ioapic.h>
-
-
-void lpc_read_resources(struct device *dev)
-{
-	struct resource *res;
-
-	printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - Start.\n");
-	/* Get the normal pci resources of this device */
-	pci_dev_read_resources(dev);	/* We got one for APIC, or one more for TRAP */
-
-	/* Add an extra subtractive resource for both memory and I/O. */
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
-	res->base = 0;
-	res->size = 0x1000;
-	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
-	res->base = 0xff800000;
-	res->size = 0x00800000; /* 8 MB for flash */
-	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
-		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	/* Add a memory resource for the SPI BAR. */
-	fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE);
-
-	res = new_resource(dev, 3);
-	res->base = IO_APIC_ADDR;
-	res->size = 0x00001000;
-	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
-	compact_resources(dev);
-	printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_read_resources - End.\n");
-}
-
-void lpc_set_resources(struct device *dev)
-{
-	struct resource *res;
-
-	printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - Start.\n");
-
-	/* Special case. SPI Base Address. The SpiRomEnable should STAY set. */
-	res = find_resource(dev, 2);
-	pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE);
-
-	pci_dev_set_resources(dev);
-
-	printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_set_resources - End.\n");
-}
-
-/**
- * @brief Enable resources for children devices
- *
- * @param dev the device whose children's resources are to be enabled
- *
- */
-void lpc_enable_childrens_resources(struct device *dev)
-{
-	struct bus *link;
-	u32 reg, reg_x;
-	int var_num = 0;
-	u16 reg_var[3];
-
-	printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - Start.\n");
-	reg = pci_read_config32(dev, 0x44);
-	reg_x = pci_read_config32(dev, 0x48);
-
-	for (link = dev->link_list; link; link = link->next) {
-		struct device *child;
-		for (child = link->children; child;
-		     child = child->sibling) {
-			if (child->enabled
-			    && (child->path.type == DEVICE_PATH_PNP)) {
-				struct resource *res;
-				for (res = child->resource_list; res; res = res->next) {
-					u32 base, end;	/*  don't need long long */
-					if (!(res->flags & IORESOURCE_IO))
-						continue;
-					base = res->base;
-					end = resource_end(res);
-/*
-					printk(BIOS_DEBUG, "sb900 lpc decode:%s, base=0x%08x, end=0x%08x\n",
-					     dev_path(child), base, end);
-*/
-					switch (base) {
-					case 0x60:	/*  KB */
-					case 0x64:	/*  MS */
-						reg |= (1 << 29);
-						break;
-					case 0x3f8:	/*  COM1 */
-						reg |= (1 << 6);
-						break;
-					case 0x2f8:	/*  COM2 */
-						reg |= (1 << 7);
-						break;
-					case 0x378:	/*  Parallel 1 */
-						reg |= (1 << 0);
-						break;
-					case 0x3f0:	/*  FD0 */
-						reg |= (1 << 26);
-						break;
-					case 0x220:	/*  Audio 0 */
-						reg |= (1 << 8);
-						break;
-					case 0x300:	/*  Midi 0 */
-						reg |= (1 << 18);
-						break;
-					case 0x400:
-						reg_x |= (1 << 16);
-						break;
-					case 0x480:
-						reg_x |= (1 << 17);
-						break;
-					case 0x500:
-						reg_x |= (1 << 18);
-						break;
-					case 0x580:
-						reg_x |= (1 << 19);
-						break;
-					case 0x4700:
-						reg_x |= (1 << 22);
-						break;
-					case 0xfd60:
-						reg_x |= (1 << 23);
-						break;
-					default:
-						if (var_num >= 3)
-							continue;	/* only 3 var ; compact them ? */
-						switch (var_num) {
-						case 0:
-							reg_x |= (1 << 2);
-							break;
-						case 1:
-							reg_x |= (1 << 24);
-							break;
-						case 2:
-							reg_x |= (1 << 25);
-							break;
-						}
-						reg_var[var_num++] =
-						    base & 0xffff;
-					}
-				}
-			}
-		}
-	}
-	pci_write_config32(dev, 0x44, reg);
-	pci_write_config32(dev, 0x48, reg_x);
-	/* Set WideIO for as many IOs found (fall through is on purpose) */
-	switch (var_num) {
-	case 3:
-		pci_write_config16(dev, 0x90, reg_var[2]);
-		/* fall through */
-	case 2:
-		pci_write_config16(dev, 0x66, reg_var[1]);
-		/* fall through */
-	case 1:
-		//pci_write_config16(dev, 0x64, reg_var[0]); //cause filo can not find sata
-		break;
-	}
-	printk(BIOS_DEBUG, "SB900 - Lpc.c - lpc_enable_childrens_resources - End.\n");
-}
--- a/src/southbridge/amd/cimx/sb900/lpc.h
+++ b/src/southbridge/amd/cimx/sb900/lpc.h
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SB900_LPC_H_
-#define _SB900_LPC_H_
-
-#define SPIROM_BASE_ADDRESS_REGISTER  0xA0
-#define SPI_ROM_ENABLE                0x02
-#define SPI_BASE_ADDRESS              0xFEC10000
-
-void lpc_read_resources(struct device *dev);
-void lpc_set_resources(struct device *dev);
-void lpc_enable_childrens_resources(struct device *dev);
-
-#endif
--- a/src/southbridge/amd/cimx/sb900/ramtop.c
+++ b/src/southbridge/amd/cimx/sb900/ramtop.c
@@ -1,43 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <arch/io.h>
-#include <cbmem.h>
-#include <southbridge/amd/cimx/cimx_util.h>
-
-void backup_top_of_low_cacheable(uintptr_t ramtop)
-{
-	u32 dword = ramtop;
-	int nvram_pos = 0xf8, i; /* temp */
-	for (i = 0; i < 4; i++) {
-		outb(nvram_pos, BIOSRAM_INDEX);
-		outb((dword >> (8 * i)) & 0xff, BIOSRAM_DATA);
-		nvram_pos++;
-	}
-}
-
-uintptr_t restore_top_of_low_cacheable(void)
-{
-	u32 xdata = 0;
-	int xnvram_pos = 0xf8, xi;
-	for (xi = 0; xi < 4; xi++) {
-		outb(xnvram_pos, BIOSRAM_INDEX);
-		xdata &= ~(0xff << (xi * 8));
-		xdata |= inb(BIOSRAM_DATA) << (xi *8);
-		xnvram_pos++;
-	}
-	return xdata;
-}
--- a/src/southbridge/amd/cimx/sb900/reset.c
+++ b/src/southbridge/amd/cimx/sb900/reset.c
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// Use simple device model for this file even in ramstage
-#define __SIMPLE_DEVICE__
-
-#include <device/pci_ops.h>
-#include <cf9_reset.h>
-#include <reset.h>
-
-#define HT_INIT_CONTROL		0x6C
-#define HTIC_BIOSR_Detect	(1<<5)
-
-#define DEV_CDB 0x18
-#define NODE_PCI(x, fn)	(((DEV_CDB+x)<32)?(PCI_DEV(0,(DEV_CDB+x),fn)):(PCI_DEV((0-1),(DEV_CDB+x-32),fn)))
-
-void cf9_reset_prepare(void)
-{
-	u32 nodes;
-	u32 htic;
-	pci_devfn_t dev;
-	int i;
-
-	nodes = ((pci_read_config32(PCI_DEV(0, DEV_CDB, 0), 0x60) >> 4) & 7) + 1;
-	for (i = 0; i < nodes; i++) {
-		dev = NODE_PCI(i, 0);
-		htic = pci_read_config32(dev, HT_INIT_CONTROL);
-		htic &= ~HTIC_BIOSR_Detect;
-		pci_write_config32(dev, HT_INIT_CONTROL, htic);
-	}
-}
-
-void do_board_reset(void)
-{
-	system_reset();
-}
--- a/src/southbridge/amd/cimx/sb900/sb_cimx.h
+++ b/src/southbridge/amd/cimx/sb900/sb_cimx.h
@@ -1,45 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#ifndef _CIMX_SB_EARLY_H_
-#define _CIMX_SB_EARLY_H_
-
-#define PM_INDEX	0xcd6
-#define PM_DATA		0xcd7
-
-#define SB900_ACPI_IO_BASE 0x800
-
-#define ACPI_PM_EVT_BLK		(SB900_ACPI_IO_BASE + 0x00) /* 4 bytes */
-#define ACPI_PM1_CNT_BLK	(SB900_ACPI_IO_BASE + 0x04) /* 2 bytes */
-#define ACPI_PMA_CNT_BLK	(SB900_ACPI_IO_BASE + 0x0F) /* 1 byte */
-#define ACPI_PM_TMR_BLK		(SB900_ACPI_IO_BASE + 0x08) /* 4 bytes */
-#define ACPI_GPE0_BLK		(SB900_ACPI_IO_BASE + 0x20) /* 8 bytes */
-#define ACPI_CPU_CONTROL	(SB900_ACPI_IO_BASE + 0x10) /* 6 bytes */
-
-#define REV_SB900_A11	0x11
-#define REV_SB900_A12	0x12
-
-/**
- * South Bridge CIMx romstage entry, sbPowerOnInit entry point wrapper.
- */
-void sb_poweron_init(void);
-void sb_before_pci_init(void);
-
-void sb_After_Pci_Init (void);
-void sb_Mid_Post_Init (void);
-void sb_Late_Post (void);
-
-#endif
--- a/src/southbridge/amd/cimx/sb900/smbus.c
+++ b/src/southbridge/amd/cimx/sb900/smbus.c
@@ -1,260 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-
-#include <arch/io.h>
-#include "smbus.h"
-#include <console/console.h>	/* printk */
-
-static int smbus_wait_until_ready(u32 smbus_io_base)
-{
-	u32 loops;
-
-	loops = SMBUS_TIMEOUT;
-	do {
-		u8 val;
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;
-		if (val == 0) {	/* ready now */
-			return 0;
-		}
-		outb(val, smbus_io_base + SMBHSTSTAT);
-	} while (--loops);
-
-	return -2;		/* time out */
-}
-
-static int smbus_wait_until_done(u32 smbus_io_base)
-{
-	u32 loops;
-
-	loops = SMBUS_TIMEOUT;
-	do {
-		u8 val;
-
-		val = inb(smbus_io_base + SMBHSTSTAT);
-		val &= 0x1f;	/* mask off reserved bits */
-		if (val & 0x1c) {
-			return -5;	/* error */
-		}
-		if (val == 0x02) {
-			outb(val, smbus_io_base + SMBHSTSTAT);	/* clear status */
-			return 0;
-		}
-	} while (--loops);
-
-	return -3;		/* timeout */
-}
-
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-	printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
-		return -2;	/* not ready */
-	}
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - Start.\n");
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTCMD);
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - End.\n");
-	return byte;
-}
-
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-	printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
-		return -2;	/* not ready */
-	}
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - Start.\n");
-	/* set the command... */
-	outb(val, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 2) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - End.\n");
-	return 0;
-}
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-	printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
-		return -2;	/* not ready */
-	}
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - Start.\n");
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-	/* read results of transaction */
-	byte = inb(smbus_io_base + SMBHSTDAT0);
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - End.\n");
-	return byte;
-}
-
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
-{
-	u8 byte;
-
-	if (smbus_wait_until_ready(smbus_io_base) < 0) {
-	printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
-		return -2;	/* not ready */
-	}
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - Start.\n");
-	/* set the command/address... */
-	outb(address & 0xff, smbus_io_base + SMBHSTCMD);
-
-	/* set the device I'm talking to */
-	outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR);
-
-	/* output value */
-	outb(val, smbus_io_base + SMBHSTDAT0);
-
-	byte = inb(smbus_io_base + SMBHSTCTRL);
-	byte &= 0xe3;		/* Clear [4:2] */
-	byte |= (1 << 3) | (1 << 6);	/* Byte data read/write command, start the command */
-	outb(byte, smbus_io_base + SMBHSTCTRL);
-
-	/* poll for transaction completion */
-	if (smbus_wait_until_done(smbus_io_base) < 0) {
-		return -3;	/* timeout or error */
-	}
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - End.\n");
-	return 0;
-}
-
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val)
-{
-	u32 tmp;
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - Start.\n");
-	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);
-	tmp = inl(AB_DATA);
-	/* rpr 4.2
-	 * For certain revisions of the chip, the ABCFG registers,
-	 * with an address of 0x100NN (where 'N' is any hexadecimal
-	 * number), require an extra programming step.*/
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */
-	outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-    printk(BIOS_INFO, "SB900 - Smbus.c - alink_ab_indx - End.\n");
-}
-
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val)
-{
-	u32 tmp;
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - Start.\n");
-	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);
-	tmp = inl(AB_DATA);
-	/* rpr 4.2
-	 * For certain revisions of the chip, the ABCFG registers,
-	 * with an address of 0x100NN (where 'N' is any hexadecimal
-	 * number), require an extra programming step.*/
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	//printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr);
-	outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX);	/* probably we don't have to do it again. */
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-    printk(BIOS_INFO, "SB900 - Smbus.c - alink_rc_indx - End.\n");
-}
-
-/* space = 0: AX_INDXC, AX_DATAC
- * space = 1: AX_INDXP, AX_DATAP
- */
-void alink_ax_indx(u32 space /*c or p? */, u32 axindc, u32 mask, u32 val)
-{
-	u32 tmp;
-
-    printk(BIOS_INFO, "SB900 - Smbus.c - alink_ax_indx - Start.\n");
-	/* read axindc to tmp */
-	outl(space << 29 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(0, AB_INDX);
-	outl(space << 29 | space << 3 | 0x34, AB_INDX);
-	tmp = inl(AB_DATA);
-	outl(0, AB_INDX);
-
-	tmp &= ~mask;
-	tmp |= val;
-
-	/* write tmp */
-	outl(space << 29 | space << 3 | 0x30, AB_INDX);
-	outl(axindc, AB_DATA);
-	outl(0, AB_INDX);
-	outl(space << 29 | space << 3 | 0x34, AB_INDX);
-	outl(tmp, AB_DATA);
-	outl(0, AB_INDX);
-    printk(BIOS_INFO, "SB900 - Smbus.c - alink_ax_indx - End.\n");
-}
--- a/src/southbridge/amd/cimx/sb900/smbus.h
+++ b/src/southbridge/amd/cimx/sb900/smbus.h
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SB900_SMBUS_H_
-#define _SB900_SMBUS_H_
-
-#define SMBUS_IO_BASE	SMBUS0_BASE_ADDRESS
-
-#define SMBHSTSTAT 0x0
-#define SMBSLVSTAT 0x1
-#define SMBHSTCTRL 0x2
-#define SMBHSTCMD  0x3
-#define SMBHSTADDR 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBHSTBLKDAT 0x7
-
-#define SMBSLVCTRL 0x8
-#define SMBSLVCMD_SHADOW 0x9
-#define SMBSLVEVT 0xa
-#define SMBSLVDAT 0xc
-
-#define AX_INDXC  0
-#define AX_INDXP  2
-#define AXCFG     4
-#define ABCFG     6
-#define RC_INDXC  1
-#define RC_INDXP  3
-
-#define AB_INDX   0xCD8
-#define AB_DATA   (AB_INDX+4)
-
-/* Between 1-10 seconds, We should never timeout normally
- * Longer than this is just painful when a timeout condition occurs.
- */
-#define SMBUS_TIMEOUT (100*1000*10)
-
-#define abcfg_reg(reg, mask, val)	\
-	alink_ab_indx((ABCFG), (reg), (mask), (val))
-#define axcfg_reg(reg, mask, val)	\
-	alink_ab_indx((AXCFG), (reg), (mask), (val))
-#define axindxc_reg(reg, mask, val)	\
-	alink_ax_indx((AX_INDXC), (reg), (mask), (val))
-#define axindxp_reg(reg, mask, val)		\
-	alink_ax_indx((AX_INDXP), (reg), (mask), (val))
-#define rcindxc_reg(reg, port, mask, val)	\
-	alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val))
-#define rcindxp_reg(reg, port, mask, val)	\
-	alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val))
-
-int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
-int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val);
-int do_smbus_recv_byte(u32 smbus_io_base, u32 device);
-int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val);
-void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val);
-void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val);
-void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val);
-
-#endif
--- a/src/southbridge/amd/cimx/sb900/smbus_spd.c
+++ b/src/southbridge/amd/cimx/sb900/smbus_spd.c
@@ -1,177 +0,0 @@
-/*****************************************************************************
- *
- * Copyright (c) 2011, Advanced Micro Devices, Inc.
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *     * Redistributions of source code must retain the above copyright
- *       notice, this list of conditions and the following disclaimer.
- *     * Redistributions in binary form must reproduce the above copyright
- *       notice, this list of conditions and the following disclaimer in the
- *       documentation and/or other materials provided with the distribution.
- *     * Neither the name of Advanced Micro Devices, Inc. nor the names of
- *       its contributors may be used to endorse or promote products derived
- *       from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ***************************************************************************/
-
-#include <Porting.h>
-#include <AGESA.h>
-#include <amdlib.h>
-
-#include <northbridge/amd/agesa/dimmSpd.h>
-
-#define SMBUS_BASE_ADDR  0xB00
-
-STATIC
-VOID
-WritePmReg (
-  IN UINT8 Reg,
-  IN UINT8 Data
-  )
-{
-   __outbyte (0xCD6, Reg);
-   __outbyte (0xCD7, Data);
-}
-STATIC
-VOID
-SetupFch (
-  IN UINT16
-  IN IoBase
-  )
-{
-   WritePmReg (0x2D, IoBase >> 8);
-   WritePmReg (0x2C, IoBase | 1);
-   WritePmReg (0x29, 0x80);
-   WritePmReg (0x28, 0x61);
-   /* set SMBus clock to 400 KHz */
-   __outbyte (IoBase + 0x0E, 66000000 / 400000 / 4);
-}
-
-/*
- *
- * ReadSmbusByteData - read a single SPD byte from any offset
- *
- */
-
-STATIC
-AGESA_STATUS
-ReadSmbusByteData (
-  IN UINT16 Iobase,
-  IN UINT8  Address,
-  OUT UINT8 *Buffer,
-  IN UINTN  Offset
-  )
-{
-   UINTN  Status;
-   UINT64 Limit;
-
-   Address |= 1; // set read bit
-
-   __outbyte (Iobase + 0, 0xFF);                // clear error status
-   __outbyte (Iobase + 1, 0x1F);                // clear error status
-   __outbyte (Iobase + 3, Offset);              // offset in eeprom
-   __outbyte (Iobase + 4, Address);             // slave address and read bit
-   __outbyte (Iobase + 2, 0x48);                // read byte command
-
-   /* time limit to avoid hanging for unexpected error status (should never happen) */
-   Limit = __rdtsc () + 2000000000 / 10;
-   for (;;) {
-     Status = __inbyte (Iobase);
-     if (__rdtsc () > Limit) break;
-     if ((Status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-     if ((Status & 1) == 1) continue;               // HostBusy set, keep waiting
-     break;
-   }
-
-   Buffer [0] = __inbyte (Iobase + 5);
-   if (Status == 2) Status = 0;                      // check for done with no errors
-   return Status;
-   }
-
-/*
- *
- * ReadSmbusByte - read a single SPD byte from the default offset
- *                 this function is faster function readSmbusByteData
- *
- */
-
-STATIC
-AGESA_STATUS
-ReadSmbusByte (
-  IN UINT16 Iobase,
-  IN UINT8  Address,
-  OUT UINT8 *Buffer
-  )
-{
-  UINTN   Status;
-  UINT64  Limit;
-
-  __outbyte (Iobase + 0, 0xFF);                // clear error status
-  __outbyte (Iobase + 2, 0x44);                // read command
-
-  // time limit to avoid hanging for unexpected error status
-  Limit = __rdtsc () + 2000000000 / 10;
-  for (;;) {
-    Status = __inbyte (Iobase);
-    if (__rdtsc () > Limit) break;
-    if ((Status & 2) == 0) continue;               // SMBusInterrupt not set, keep waiting
-    if ((Status & 1) == 1) continue;               // HostBusy set, keep waiting
-    break;
-  }
-
-  Buffer [0] = __inbyte (Iobase + 5);
-  if (Status == 2) Status = 0;                      // check for done with no errors
-  return Status;
-}
-
-/*
- *
- * ReadSpd - Read one or more SPD bytes from a DIMM.
- *           Start with offset zero and read sequentially.
- *           Optimization relies on autoincrement to avoid
- *           sending offset for every byte.
- *           Reads 128 bytes in 7-8 ms at 400 KHz.
- *
- */
-
-STATIC
-AGESA_STATUS
-ReadSpd (
-  IN UINT16 IoBase,
-  IN UINT8  SmbusSlaveAddress,
-  OUT UINT8 *Buffer,
-  IN UINTN  Count
-  )
-{
-  UINTN Index, Status;
-
-  /* read the first byte using offset zero */
-  Status = ReadSmbusByteData (IoBase, SmbusSlaveAddress, Buffer, 0);
-  if (Status) return Status;
-
-  /* read the remaining bytes using auto-increment for speed */
-  for (Index = 1; Index < Count; Index++){
-    Status = ReadSmbusByte (IoBase, SmbusSlaveAddress, &Buffer [Index]);
-    if (Status) return Status;
-  }
-  return 0;
-}
-
-int smbus_readSpd(int spdAddress, char *buf, size_t len)
-{
-   SetupFch (SMBUS_BASE_ADDR);
-   return ReadSpd (SMBUS_BASE_ADDR, spdAddress, (UINT8 *) buf, len);
-}