cpu/intel: Make all Intel CPUs load microcode from CBFS
The sequence to inject microcode updates is virtually the same for all Intel CPUs. The same function is used to inject the update in both CBFS and hardcoded cases, and in both of these cases, the microcode resides in the ROM. This should be a safe change across the board. The function which loaded compiled-in microcode is also removed here in order to prevent it from being used in the future. The dummy terminators from microcode need to be removed if this change is to work when generating microcode from several microcode_blob.c files, as is the case for older socketed CPUs. Removal of dummy terminators is done in a subsequent patch. Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4495 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@gmail.com>
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@ -1,3 +1,4 @@
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config CPU_INTEL_MODEL_67X
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bool
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select SMP
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select SUPPORT_CPU_UCODE_IN_CBFS
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@ -20,3 +20,4 @@
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ramstage-y += model_67x_init.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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13
src/cpu/intel/model_67x/microcode_blob.c
Normal file
13
src/cpu/intel/model_67x/microcode_blob.c
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@ -0,0 +1,13 @@
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unsigned microcode_updates_67x[] = {
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/* Include microcode updates here. */
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#include "microcode-293-MU267114.h"
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#include "microcode-530-MU16730e.h"
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#include "microcode-531-MU26732e.h"
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#include "microcode-539-MU167210.h"
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#include "microcode-540-MU267238.h"
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/* Dummy terminator */
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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};
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@ -29,24 +29,10 @@
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#include <cpu/x86/msr.h>
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#include <cpu/intel/l2_cache.h>
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static const uint32_t microcode_updates[] = {
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/* Include microcode updates here. */
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#include "microcode-293-MU267114.h"
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#include "microcode-530-MU16730e.h"
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#include "microcode-531-MU26732e.h"
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#include "microcode-539-MU167210.h"
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#include "microcode-540-MU267238.h"
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/* Dummy terminator */
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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0x0, 0x0, 0x0, 0x0,
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};
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static void model_67x_init(device_t cpu)
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{
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/* Update the microcode */
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intel_update_microcode(microcode_updates);
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intel_update_microcode_from_cbfs();
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/* Initialize L2 cache */
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p6_configure_l2_cache();
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