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cpu/intel: Make all Intel CPUs load microcode from CBFS

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The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.

The function which loaded compiled-in microcode is also removed here in
order to prevent it from being used in the future.

The dummy terminators from microcode need to be removed if this change is
to work when generating microcode from several microcode_blob.c files, as
is the case for older socketed CPUs. Removal of dummy terminators is done
in a subsequent patch.

Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This commit is contained in:
Alexandru Gagniuc
2013-12-06 23:14:54 -06:00
parent b4c39902ed
commit 2c38f50b4a
73 changed files with 390 additions and 438 deletions
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12
src/cpu/intel/slot_1/Kconfig
View File

@@ -19,10 +19,20 @@
config CPU_INTEL_SLOT_1
bool
if CPU_INTEL_SLOT_1
config SLOT_SPECIFIC_OPTIONS # dummy
def_bool y
select CACHE_AS_RAM
select CPU_INTEL_MODEL_65X
select CPU_INTEL_MODEL_67X
select CPU_INTEL_MODEL_68X
select CPU_INTEL_MODEL_6BX
select CPU_INTEL_MODEL_6XX
config DCACHE_RAM_SIZE
hex
default 0x01000
depends on CPU_INTEL_SLOT_1
endif