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mb/google/brya: Disable PCH USB2 phy power gating for felwinter

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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for felwinter board. Please refer Intel doc#723158 for
more information.

BUG=b:221461379, b:226020977
TEST=Verify the build for felwinter board

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I25033ea218fa3154eb99af6be43c4198f4db3bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Sridhar Siricilla
2022-04-02 10:42:47 +05:30
committed by Felix Held
parent 5215f2ffcb
commit 2c4b426557
1 changed files with 4 additions and 0 deletions
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4
src/mainboard/google/brya/variants/felwinter/overridetree.cb
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@@ -44,6 +44,10 @@ chip soc/intel/alderlake
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
}" }"
# As per Intel Advisory doc#723158, the change is required to prevent possible
# display flickering issue.
register "usb2_phy_sus_pg_disable" = "1"
# Intel Common SoC Config # Intel Common SoC Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |