soc/intel/cannonlake/chip.h: Use boolean type where applicable
Change-Id: If9639bd1d0737f94931c28b0e12f214a5c1f87c0 Signed-off-by: lilacious <yuchenhe126@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75959 Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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lilacious
Felix Singer
parent
552da5685e
commit
2c7b6eb9c9
@ -10,6 +10,7 @@
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#include <intelblocks/gspi.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/power_limit.h>
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#include <stdbool.h>
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#include <stdint.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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@ -57,12 +58,12 @@ struct soc_intel_cannonlake_config {
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/* S0ix configuration */
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/* Enable S0iX support */
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int s0ix_enable;
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bool s0ix_enable;
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/* Enable Audio DSP oscillator qualification for S0ix */
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uint8_t cppmvric2_adsposcdis;
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bool cppmvric2_adsposcdis;
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/* Enable DPTF support */
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int dptf_enable;
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bool dptf_enable;
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enum {
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MAX_PC_DEFAULT = 0,
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@ -78,10 +79,10 @@ struct soc_intel_cannonlake_config {
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} max_package_c_state;
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/* Deep SX enable for both AC and DC */
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int deep_s3_enable_ac;
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int deep_s3_enable_dc;
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int deep_s5_enable_ac;
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int deep_s5_enable_dc;
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bool deep_s3_enable_ac;
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bool deep_s3_enable_dc;
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bool deep_s5_enable_ac;
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bool deep_s5_enable_dc;
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/* Deep Sx Configuration
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* DSX_EN_WAKE_PIN - Enable WAKE# pin
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@ -107,7 +108,7 @@ struct soc_intel_cannonlake_config {
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} SaGv;
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/* Rank Margin Tool. 1:Enable, 0:Disable */
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uint8_t RMT;
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bool RMT;
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/* USB related */
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struct usb2_port_config usb2_ports[16];
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@ -117,7 +118,7 @@ struct soc_intel_cannonlake_config {
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/* Wake Enable Bitmap for USB3 ports */
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uint16_t usb3_wake_enable_bitmap;
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/* USB2 PHY power gating */
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uint8_t PchUsb2PhySusPgDisable;
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bool PchUsb2PhySusPgDisable;
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/* SATA related */
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enum {
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@ -133,39 +134,39 @@ struct soc_intel_cannonlake_config {
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SataDevSlpDswReset = 7
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} SataDevSlpRstConfig;
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uint8_t SataSalpSupport;
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uint8_t SataPortsEnable[8];
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uint8_t SataPortsDevSlp[8];
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bool SataSalpSupport;
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bool SataPortsEnable[8];
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bool SataPortsDevSlp[8];
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uint8_t SataPortsDevSlpResetConfig[8];
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uint8_t SataPortsHotPlug[8];
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bool SataPortsHotPlug[8];
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/* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */
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uint8_t SlpS0WithGbeSupport;
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bool SlpS0WithGbeSupport;
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/* SLP_S0 Voltage Margining Policy. 0: disable, 1: enable */
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uint8_t PchPmSlpS0VmRuntimeControl;
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bool PchPmSlpS0VmRuntimeControl;
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/* SLP_S0 Voltage Margining 0.70V Policy. 0: disable, 1: enable */
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uint8_t PchPmSlpS0Vm070VSupport;
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bool PchPmSlpS0Vm070VSupport;
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/* SLP_S0 Voltage Margining 0.75V Policy. 0: disable, 1: enable */
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uint8_t PchPmSlpS0Vm075VSupport;
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bool PchPmSlpS0Vm075VSupport;
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/* Audio related */
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uint8_t PchHdaDspEnable;
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bool PchHdaDspEnable;
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/* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */
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uint8_t PchHdaAudioLinkHda;
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uint8_t PchHdaIDispCodecDisconnect;
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uint8_t PchHdaAudioLinkDmic0;
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uint8_t PchHdaAudioLinkDmic1;
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uint8_t PchHdaAudioLinkSsp0;
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uint8_t PchHdaAudioLinkSsp1;
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uint8_t PchHdaAudioLinkSsp2;
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uint8_t PchHdaAudioLinkSndw1;
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uint8_t PchHdaAudioLinkSndw2;
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uint8_t PchHdaAudioLinkSndw3;
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uint8_t PchHdaAudioLinkSndw4;
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bool PchHdaAudioLinkHda;
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bool PchHdaIDispCodecDisconnect;
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bool PchHdaAudioLinkDmic0;
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bool PchHdaAudioLinkDmic1;
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bool PchHdaAudioLinkSsp0;
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bool PchHdaAudioLinkSsp1;
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bool PchHdaAudioLinkSsp2;
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bool PchHdaAudioLinkSndw1;
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bool PchHdaAudioLinkSndw2;
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bool PchHdaAudioLinkSndw3;
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bool PchHdaAudioLinkSndw4;
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/* PCIe Root Ports */
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uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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/* PCIe output clocks type to PCIe devices.
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* 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use,
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* 0xFF: not used */
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@ -174,18 +175,18 @@ struct soc_intel_cannonlake_config {
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* clksrc. */
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uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCK_SRC];
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/* PCIe LTR(Latency Tolerance Reporting) mechanism */
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uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS];
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/* Implemented as slot or built-in? */
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uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
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/* Enable/Disable HotPlug support for Root Port */
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uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
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/*
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* Enable/Disable AER (Advanced Error Reporting) for Root Port
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* 0: Disable AER
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* 1: Enable AER
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*/
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uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
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bool PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS];
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/* PCIE RP ASPM, ASPM support for the root port */
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enum {
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@ -204,23 +205,23 @@ struct soc_intel_cannonlake_config {
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} PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS];
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/* eMMC and SD */
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uint8_t ScsEmmcHs400Enabled;
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bool ScsEmmcHs400Enabled;
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/* Need to update DLL setting to get Emmc running at HS400 speed */
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uint8_t EmmcHs400DllNeed;
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bool EmmcHs400DllNeed;
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/* 0-39: number of active delay for RX strobe, unit is 125 psec */
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uint8_t EmmcHs400RxStrobeDll1;
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/* 0-78: number of active delay for TX data, unit is 125 psec */
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uint8_t EmmcHs400TxDataDll;
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/* Enable/disable SD card write protect pin configuration on CML */
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uint8_t ScsSdCardWpPinEnabled;
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bool ScsSdCardWpPinEnabled;
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/* Heci related */
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uint8_t DisableHeciRetry;
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bool DisableHeciRetry;
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/* Gfx related */
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uint8_t SkipExtGfxScan;
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bool SkipExtGfxScan;
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uint8_t Device4Enable;
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bool Device4Enable;
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/* CPU PL2/4 Config
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* Performance: Maximum PLs for maximum performance.
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@ -234,13 +235,13 @@ struct soc_intel_cannonlake_config {
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struct vr_config domain_vr_config[NUM_VR_DOMAINS];
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/* Enables support for Teton Glacier hybrid storage device */
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uint8_t TetonGlacierMode;
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bool TetonGlacierMode;
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/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
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uint8_t eist_enable;
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bool eist_enable;
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/* Enable C6 DRAM */
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uint8_t enable_c6dram;
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bool enable_c6dram;
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/*
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* SLP_S3 Minimum Assertion Width Policy
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@ -346,14 +347,14 @@ struct soc_intel_cannonlake_config {
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unsigned int sdcard_cd_gpio;
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/* Enable Pch iSCLK */
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uint8_t pch_isclk;
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bool pch_isclk;
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/*
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* Acoustic Noise Mitigation
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* 0b - Disable
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* 1b - Enable noise mitigation
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*/
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uint8_t AcousticNoiseMitigation;
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bool AcousticNoiseMitigation;
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/*
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* Disable Fast Package C-state ramping
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@ -361,10 +362,10 @@ struct soc_intel_cannonlake_config {
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* 0b - Enabled
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* 1b - Disabled
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*/
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uint8_t FastPkgCRampDisableIa;
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uint8_t FastPkgCRampDisableGt;
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uint8_t FastPkgCRampDisableSa;
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uint8_t FastPkgCRampDisableFivr;
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bool FastPkgCRampDisableIa;
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bool FastPkgCRampDisableGt;
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bool FastPkgCRampDisableSa;
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bool FastPkgCRampDisableFivr;
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/*
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* Adjust the VR slew rates
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@ -380,32 +381,32 @@ struct soc_intel_cannonlake_config {
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uint8_t SlowSlewRateForFivr;
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/* SATA Power Optimizer */
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uint8_t satapwroptimize;
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bool satapwroptimize;
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/* SATA Gen3 Strength */
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struct sata_port_config sata_port[SOC_INTEL_CML_SATA_DEV_MAX];
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/* Enable or disable eDP device */
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uint8_t DdiPortEdp;
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bool DdiPortEdp;
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/* Enable or disable HPD of DDI port B/C/D/F */
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uint8_t DdiPortBHpd;
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uint8_t DdiPortCHpd;
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uint8_t DdiPortDHpd;
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uint8_t DdiPortFHpd;
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bool DdiPortBHpd;
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bool DdiPortCHpd;
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bool DdiPortDHpd;
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bool DdiPortFHpd;
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/* Enable or disable DDC of DDI port B/C/D/F */
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uint8_t DdiPortBDdc;
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uint8_t DdiPortCDdc;
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uint8_t DdiPortDDdc;
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uint8_t DdiPortFDdc;
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bool DdiPortBDdc;
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bool DdiPortCDdc;
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bool DdiPortDDdc;
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bool DdiPortFDdc;
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/* Unlock all GPIO Pads */
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uint8_t PchUnlockGpioPads;
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bool PchUnlockGpioPads;
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/* Enable GBE wakeup */
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uint8_t LanWakeFromDeepSx;
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uint8_t WolEnableOverride;
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bool LanWakeFromDeepSx;
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bool WolEnableOverride;
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#if !CONFIG(SOC_INTEL_COMETLAKE)
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uint32_t VrPowerDeliveryDesign;
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@ -416,7 +417,7 @@ struct soc_intel_cannonlake_config {
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* 0: Use FSP default GPIO PM program,
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* 1: coreboot to override GPIO PM program
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*/
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uint8_t gpio_override_pm;
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bool gpio_override_pm;
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/*
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* GPIO PM configuration: 0 to disable, 1 to enable power gating
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* Bit 6-7: Reserved
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