Add AMD C32 support.

It is based on other existing Fam10 code.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/cpu/amd/socket_C32/Kconfig

@@ -0,0 +1,42 @@
+config CPU_AMD_SOCKET_C32
+	bool
+	select CPU_AMD_MODEL_10XXX
+	select HT3_SUPPORT
+	select PCI_IO_CFG_EXT
+	select CACHE_AS_RAM
+
+config CPU_SOCKET_TYPE
+	hex
+	default 0x14
+	depends on CPU_AMD_SOCKET_C32
+
+config EXT_RT_TBL_SUPPORT
+	bool
+	default n
+	depends on CPU_AMD_SOCKET_C32
+
+config EXT_CONF_SUPPORT
+	bool
+	default n
+	depends on CPU_AMD_SOCKET_C32
+
+config CBB
+	hex
+	default 0x0
+	depends on CPU_AMD_SOCKET_C32
+
+config CDB
+	hex
+	default 0x18
+	depends on CPU_AMD_SOCKET_C32
+
+config XIP_ROM_BASE
+	hex
+	default 0xfff80000
+	depends on CPU_AMD_SOCKET_C32
+
+config XIP_ROM_SIZE
+	hex
+	default 0x80000
+	depends on CPU_AMD_SOCKET_C32
+

src/cpu/amd/socket_C32/Makefile.inc

@@ -0,0 +1,14 @@
+ramstage-y += socket_C32.c
+subdirs-y += ../model_10xxx
+subdirs-y += ../quadcore
+subdirs-y += ../mtrr
+subdirs-y += ../microcode
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/pae
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/smm
+subdirs-y += ../smm
+
+cpu_incs += $(src)/cpu/amd/car/cache_as_ram.inc

src/cpu/amd/socket_C32/chip.h

@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_amd_socket_C32_ops;
+
+struct cpu_amd_socket_C32_config {
+};

src/cpu/amd/socket_C32/socket_C32.c

@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_amd_socket_C32_ops = {
+	CHIP_NAME("socket C32")
+};