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soc/intel/common/block/cse: Move me_read_config32() to common code

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me_read_config32() is defined in multiple places, move it to common
location. Also, this function is usually used for reading HFSTS
registers, hence move the HFSTS register definitions to common location.

Also add a funtion to check if the CSE device has been enabled in the
devicetree and it is visible on the bus. This API can be used by
the caller to check before initiating any HECI communication.

TEST=Verified reading HFSTS registers on CML RVP & Hatch board

Change-Id: Icdbfb6b30a007d469b5e018a313c14586addb130
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35225
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sridhar Siricilla
2019-08-31 11:20:34 +05:30
committed by Subrata Banik
parent 910490f3f4
commit 2cc66916e5
6 changed files with 63 additions and 31 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/soc/intel/apollolake/cse.c
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@@ -28,12 +28,6 @@
#include <device/pci_ops.h>
#include <stdint.h>
#define PCI_ME_HFSTS1 0x40
#define PCI_ME_HFSTS2 0x48
#define PCI_ME_HFSTS3 0x60
#define PCI_ME_HFSTS4 0x64
#define PCI_ME_HFSTS5 0x68
#define PCI_ME_HFSTS6 0x6c
#define MKHI_GROUP_ID_MCA 0x0a
#define READ_FILE 0x02
@@ -188,7 +182,9 @@ static void fpf_blown(void *unused)
static uint32_t dump_status(int index, int reg_addr)
{
uint32_t reg = pci_read_config32(PCH_DEV_CSE, reg_addr);
uint32_t reg;
reg = me_read_config32(reg_addr);
printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg);
@@ -256,6 +252,9 @@ static void dump_cse_state(void)
{
uint32_t fwsts1;
if (!is_cse_enabled())
return;
fwsts1 = dump_status(1, PCI_ME_HFSTS1);
dump_status(2, PCI_ME_HFSTS2);
dump_status(3, PCI_ME_HFSTS3);