sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/common/block/espi_util: Refactor eSPI Setup

Browse Source 
eSPI is setup in two different locations in bootblock depending on early
port80 routing configuration. Also eSPI is setup in PSP, if verified
boot starts before bootblock. Consolidate all the scenarios by
initializating eSPI very early in fch_pre_init if verified boot starts
after bootblock and eSPI is enabled.

BUG=None
TEST=Build and boot to OS in Guybrush. Perform S5->S0, G3->S0, warm
reset and suspend/resume cycles for 50 iterations each.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Icfeba17dae0a964c9ca73686e29c18d965589934
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Karthikeyan Ramasubramanian
2021-10-05 13:57:30 -06:00
committed by Felix Held
parent 425e73d3f5
commit 2d17ea4d50
5 changed files with 17 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/amd/picasso/early_fch.c
View File

@@ -45,7 +45,10 @@ void fch_pre_init(void)
/* Enable_acpimmio_decode_pm04 to enable the ACPIMMIO decode which is needed to access
the GPIO registers. */
enable_acpimmio_decode_pm04();
/* Setup SPI base by calling lpc_early_init before setting up eSPI. */
lpc_early_init();
/* Setup eSPI to enable port80 routing. */
configure_espi();
if (!CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
lpc_configure_decodes();
@@ -81,7 +84,4 @@ void fch_early_init(void)
if (CONFIG(DISABLE_SPI_FLASH_ROM_SHARING))
lpc_disable_spi_rom_sharing();
if (CONFIG(SOC_AMD_COMMON_BLOCK_USE_ESPI))
espi_setup();
}