sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/i945: Switch to POSTCAR_STAGE

Browse Source 
Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Arthur Heymans
2018-06-03 10:39:16 +02:00
parent 3aa9adba67
commit 2dcc3a5c68
5 changed files with 12 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/intel/socket_441/Makefile.inc
View File

@@ -8,10 +8,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/car/cache_as_ram_ht.inc
else
cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S postcar-y += ../car/p4-netburst/exit_car.S
endif
romstage-y += ../car/romstage.c romstage-y += ../car/romstage.c

4
src/cpu/intel/socket_mFCPGA478/Makefile.inc
View File

@@ -11,11 +11,7 @@ subdirs-y += ../microcode
subdirs-y += ../hyperthreading subdirs-y += ../hyperthreading
subdirs-y += ../speedstep subdirs-y += ../speedstep
ifneq ($(CONFIG_POSTCAR_STAGE),y)
cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
else
cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S
postcar-y += ../car/p4-netburst/exit_car.S postcar-y += ../car/p4-netburst/exit_car.S
endif
romstage-y += ../car/romstage.c romstage-y += ../car/romstage.c

2
src/northbridge/intel/i945/Kconfig
View File

@@ -28,6 +28,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
select RELOCATABLE_RAMSTAGE select RELOCATABLE_RAMSTAGE
select INTEL_EDID select INTEL_EDID
select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT
select POSTCAR_STAGE
select POSTCAR_CONSOLE
config NORTHBRIDGE_INTEL_SUBTYPE_I945GC config NORTHBRIDGE_INTEL_SUBTYPE_I945GC
def_bool n def_bool n

2
src/northbridge/intel/i945/Makefile.inc
View File

@@ -29,4 +29,6 @@ romstage-y += rcven.c
smm-y += udelay.c smm-y += udelay.c
postcar-y += ram_calc.c
endif endif

14
src/northbridge/intel/i945/ram_calc.c
View File

@@ -80,9 +80,10 @@ u32 decode_igd_memory_size(const u32 gms)
#define ROMSTAGE_RAM_STACK_SIZE 0x5000 #define ROMSTAGE_RAM_STACK_SIZE 0x5000
/* setup_stack_and_mtrrs() determines the stack to use after /* platform_enter_postcar() determines the stack to use after
* cache-as-ram is torn down as well as the MTRR settings to use. */ * cache-as-ram is torn down as well as the MTRR settings to use,
void *setup_stack_and_mtrrs(void) * and continues execution in postcar stage. */
void platform_enter_postcar(void)
{ {
struct postcar_frame pcf; struct postcar_frame pcf;
uintptr_t top_of_ram; uintptr_t top_of_ram;
@@ -105,8 +106,7 @@ void *setup_stack_and_mtrrs(void)
postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK);
postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK);
/* Save the number of MTRRs to setup. Return the stack location run_postcar_phase(&pcf);
* pointing to the number of MTRRs.
*/ /* We do not return here. */
return postcar_commit_mtrrs(&pcf);
} }