cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Martin Roth
Martin Roth
@ -28,6 +28,7 @@ if CPU_INTEL_FSP_MODEL_206AX || CPU_INTEL_FSP_MODEL_306AX
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select PLATFORM_USES_FSP
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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@ -70,26 +71,4 @@ config MICROCODE_INCLUDE_PATH
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default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX
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default "../intel/cpu/sandybridge/microcode" if CPU_INTEL_FSP_MODEL_206AX
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config FSP_IMAGE_ID_DWORD0
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hex
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default 0x2D325453 if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_I89XX
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default 0x2D324343 if CPU_INTEL_FSP_MODEL_306AX && SOUTHBRIDGE_INTEL_FSP_BD82X6X
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help
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The FSP Image ID is different for each platform's FSP and can be used to
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verify that the right FSP binary is loaded.
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For the ivybridge/89xx FSP, the Image Id will be "ST2-FSP\0",
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for ivybridge/bd82x6x FSPs, the Image Id will be "CC2-FSP\0",
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This dword holds the first 4 bytes of the string, as
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a hex value.
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config FSP_IMAGE_ID_DWORD1
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hex
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default 0x00505346
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help
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For the ivybridge/I89xx FSP, the Image Id will be "ST2-FSP\0",
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for ivybridge/bd82x6x FSPs, the Image Id will be "CC2-FSP\0",
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This dword holds the second 4 bytes of the string, as
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a hex value. Since the strings use the same second dword,
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no additional logic is needed.
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endif
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@ -7,9 +7,8 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
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cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c
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cpu_incs += $(src)/cpu/intel/fsp_model_206ax/cache_as_ram.inc
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CC_bootblock := $(CC_bootblock) -I$(CONFIG_MICROCODE_INCLUDE_PATH)
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CC_romstage := $(CC_romstage) -I$(CONFIG_MICROCODE_INCLUDE_PATH)
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CC_ramstage := $(CC_ramstage) -I$(CONFIG_MICROCODE_INCLUDE_PATH)
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CC_x86_32 := $(CC_x86_32) -I$(CONFIG_MICROCODE_INCLUDE_PATH)
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ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),)
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ifneq ($(wildcard $(shell realpath -L "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),)
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INCLUDES += -I$(CONFIG_MICROCODE_INCLUDE_PATH)
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endif
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endif
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@ -1,292 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2013 Sage Electronic Engineering, LLC.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cpu/x86/stack.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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#include <cbmem.h>
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#define CPU_PHYSMASK_HI (1 << (CONFIG_CPU_ADDR_BITS - 32) - 1)
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#define LHLT_DELAY 0x50000 /* delay between post codes on FSP failure */
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#define NoEvictMod_MSR 0x2e0
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cache_as_ram:
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post_code(0x20)
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/* Send INIT IPI to all excluding ourself. */
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movl $0x000C4500, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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/* All CPUs need to be in Wait for SIPI state */
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wait_for_sipi:
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movl (%esi), %eax
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bt $12, %eax
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jc wait_for_sipi
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post_code(0x21)
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/* Zero out all fixed range and variable range MTRRs. */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) / 2), %edi
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xorl %eax, %eax
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xorl %edx, %edx
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clear_mtrrs:
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movw (%esi), %bx
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movzx %bx, %ecx
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wrmsr
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add $2, %esi
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dec %edi
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jnz clear_mtrrs
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/* Init floating point */
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emms
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fninit
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/*
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* Find the FSP binary in cbfs.
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* Make a fake stack that has the return value back to this code.
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*/
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lea fake_fsp_stack, %esp
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jmp find_fsp
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find_fsp_ret:
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/* Save the FSP location */
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mov %eax, %ebp
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cmp $CONFIG_FSP_LOC, %eax
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jb halt1
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post_code(0x22)
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/* Calculate entry into FSP */
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mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
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add 0x1c(%ebp), %eax /* add in the offset for the FSP base address */
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/*
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* Pass early init variables on a fake stack (no memory yet)
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* as well as the return location
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*/
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lea CAR_init_stack, %esp
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/* call FSP binary to setup temporary stack */
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jmp *%eax
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CAR_init_done:
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addl $4, %esp
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cmp $0, %eax
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jne halt2
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/* Save FSP_INFO_HEADER location in ebx */
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mov %ebp, %ebx
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/*
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* setup bootloader stack
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* ecx: stack base
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* edx: stack top
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*/
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lea -4(%edx), %esp
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movl %esp, %ebp
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before_romstage:
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post_code(0x23)
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/* Call romstage.c main function. */
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pushl %ebx
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call main
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romstage_main_return:
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post_code(0x2f)
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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post_code(0x31)
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/* Disable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(~MTRRdefTypeEn), %eax
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wrmsr
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post_code(0x32)
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/* Zero out all fixed range and variable range MTRRs. */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) / 2), %edi
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xorl %eax, %eax
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xorl %edx, %edx
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_clear_mtrrs_:
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movw (%esi), %bx
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movzx %bx, %ecx
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wrmsr
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add $2, %esi
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dec %edi
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jnz _clear_mtrrs_
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post_code(0x33)
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/* Enable cache. */
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movl %cr0, %eax
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andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
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movl %eax, %cr0
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post_code(0x36)
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/* Disable cache. */
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movl %cr0, %eax
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orl $CR0_CacheDisable, %eax
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movl %eax, %cr0
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post_code(0x38)
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/* Enable Write Back and Speculative Reads for the first MB
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* and ramstage.
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*/
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movl $MTRRphysBase_MSR(0), %ecx
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movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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movl $MTRRphysMask_MSR(0), %ecx
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movl $(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
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movl $CPU_PHYSMASK_HI, %edx // 36bit address space
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wrmsr
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#if CACHE_ROM_SIZE
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/* Enable Caching and speculative Reads for the
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* complete ROM now that we actually have RAM.
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*/
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movl $MTRRphysBase_MSR(1), %ecx
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movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
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xorl %edx, %edx
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wrmsr
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movl $MTRRphysMask_MSR(1), %ecx
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movl $(~(CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
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movl $CPU_PHYSMASK_HI, %edx
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wrmsr
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#endif
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post_code(0x39)
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/* And enable cache again after setting MTRRs. */
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movl %cr0, %eax
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andl $~(CR0_CacheDisable | CR0_NoWriteThrough), %eax
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movl %eax, %cr0
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post_code(0x3a)
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/* Enable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $MTRRdefTypeEn, %eax
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wrmsr
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post_code(0x3d)
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/* Clear boot_complete flag. */
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xorl %ebp, %ebp
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__main:
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post_code(POST_PREPARE_RAMSTAGE)
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cld /* Clear direction flag. */
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movl %ebp, %esi
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movl $ROMSTAGE_STACK, %esp
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movl %esp, %ebp
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pushl %esi
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call copy_and_run
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halt1:
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/*
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* Failures for postcode 0xBA - failed in find_fsp()
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*
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* Values are:
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* 0x01 - FV signature, "_FVH" not present
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* 0x02 - FFS GUID not present
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* 0x03 - FSP INFO Header not found
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* 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
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* a different location, or does it need to be?
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* 0x05 - FSP INFO Header signature "FSPH" not found
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* 0x06 - FSP Image ID is not the expected ID.
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* For ivybridge_bd82x6x, the ID is expected to be 'CC2-FSP\0'
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* For ivybridge_i89xx, the ID is expected to be 'ST2-FSP\0'
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*
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*/
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movb $0xBA, %ah
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jmp .Lhlt
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halt2:
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/*
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* Failures for postcode 0xBB - failed in the FSP:
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*
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* 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
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* 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
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* 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
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* 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
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* 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
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* 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
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*/
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movb $0xBB, %ah
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.Lhlt:
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xchg %al, %ah
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#if CONFIG_POST_IO
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outb %al, $CONFIG_POST_IO_PORT
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#else
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post_code(POST_DEAD_CODE)
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#endif
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movl $LHLT_DELAY, %ecx
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.Lhlt_Delay:
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outb %al, $0xED
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loop .Lhlt_Delay
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jmp .Lhlt
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.align 4
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fake_fsp_stack:
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.long find_fsp_ret
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CAR_init_params:
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.long CONFIG_CPU_MICROCODE_CBFS_LOC
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.long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
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.long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
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.long CONFIG_ROM_SIZE /* Total Firmware Length */
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CAR_init_stack:
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.long CAR_init_done
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.long CAR_init_params
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mtrr_table:
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/* Fixed MTRRs */
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.word 0x250, 0x258, 0x259
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.word 0x268, 0x269, 0x26A
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.word 0x26B, 0x26C, 0x26D
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.word 0x26E, 0x26F
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/* Variable MTRRs */
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.word 0x200, 0x201, 0x202, 0x203
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.word 0x204, 0x205, 0x206, 0x207
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.word 0x208, 0x209, 0x20A, 0x20B
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.word 0x20C, 0x20D, 0x20E, 0x20F
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/* .word 0x210, 0x211, 0x212, 0x213 */
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mtrr_table_end:
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