soc/intel/cannonlake: Clear PMCON status bits

The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.

BUG=b:128482282
BRANCH=None
TEST=In cbmem logs, check for value of “prev_sleep_state” using command
cbmem –c | grep “prev_sleep_state”

For cold reboot, "prev_sleep_state 5"
For warm reboot, "prev_sleep_state 0"

Change-Id: If9863d52ed3c61b6a160df53f023b0787eaaed68
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>

src/soc/intel/cannonlake/finalize.c

@@ -85,6 +85,8 @@ static void pch_finalize(void)
 	}
 
 	pch_handle_sideband(config);
+
+	pmc_clear_pmcon_sts();
 }
 
 static void soc_finalize(void *unused)