cpu/amd/pi/00630F01: Remove unused directory and code
No board currently uses AMD PI 00630F01 so remove it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: If270c2a979346029748230952caba78a5e763d75 Reviewed-on: https://review.coreboot.org/c/coreboot/+/53993 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Michał Żygowski
Felix Held
parent
8dd5b17c7a
commit
2de78e25a3
@ -1,13 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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config CPU_AMD_PI_00630F01
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bool
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select X86_AMD_FIXED_MTRRS
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if CPU_AMD_PI_00630F01
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config CPU_ADDR_BITS
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int
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default 48
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endif
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@ -1,17 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0-only
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romstage-y += fixme.c
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ramstage-y += fixme.c
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ramstage-y += chip_name.c
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ramstage-y += model_15_init.c
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smm-y += udelay.c
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subdirs-y += ../../mtrr
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subdirs-y += ../../smm
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subdirs-y += ../../../x86/tsc
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subdirs-y += ../../../x86/lapic
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subdirs-y += ../../../x86/cache
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subdirs-y += ../../../x86/mtrr
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subdirs-y += ../../../x86/pae
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@ -1,48 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Processor Object
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*
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*/
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Scope (\_SB) { /* define processor scope */
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Device (P000) {
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Name(_HID, "ACPI0007")
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Name(_UID, 0)
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}
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Device (P001) {
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Name(_HID, "ACPI0007")
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Name(_UID, 1)
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}
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Device (P002) {
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Name(_HID, "ACPI0007")
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Name(_UID, 2)
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}
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Device (P003) {
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Name(_HID, "ACPI0007")
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Name(_UID, 3)
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}
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Device (P004) {
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Name(_HID, "ACPI0007")
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Name(_UID, 4)
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}
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Device (P005) {
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Name(_HID, "ACPI0007")
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Name(_UID, 5)
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}
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Device (P006) {
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Name(_HID, "ACPI0007")
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Name(_UID, 6)
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}
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Device (P007) {
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Name(_HID, "ACPI0007")
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Name(_UID, 7)
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}
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} /* End _SB scope */
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@ -1,7 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <device/device.h>
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struct chip_operations cpu_amd_pi_00630F01_ops = {
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CHIP_NAME("AMD CPU Family 15h Model 30h-3Fh")
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};
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@ -1,56 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#include <Porting.h>
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#include <AGESA.h>
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#include <amdlib.h>
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void amd_initcpuio(void)
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{
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UINT64 MsrReg;
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UINT32 PciData;
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PCI_ADDR PciAddress;
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AMD_CONFIG_PARAMS StdHeader;
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/* Enable legacy video routing: D18F1xF4 VGA Enable */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4);
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PciData = 1;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* The platform BIOS needs to ensure the memory ranges of Hudson legacy
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* devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are
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* set to non-posted regions.
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*/
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84);
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/* last address before processor local APIC at FEE00000 */
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PciData = 0x00FEDF00;
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/* set NP (non-posted) bit */
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PciData |= 1 << 7;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80);
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/* lowest NP address is HPET at FED00000 */
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PciData = (0xFED00000 >> 8) | 3;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Map the remaining PCI hole as posted MMIO */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C);
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/* last address before non-posted range */
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PciData = 0x00FECF00;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader);
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MsrReg = (MsrReg >> 8) | 3;
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88);
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PciData = (UINT32)MsrReg;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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/* Send all IO (0000-FFFF) to southbridge. */
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4);
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PciData = 0x0000F000;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0);
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PciData = 0x00000003;
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LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader);
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}
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@ -1,121 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <console/console.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/amd/mtrr.h>
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#include <cpu/x86/smm.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <cpu/x86/pae.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/cache.h>
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static void model_15_init(struct device *dev)
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{
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printk(BIOS_DEBUG, "Model 15 Init.\n");
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u8 i;
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msr_t msr;
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int num_banks;
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int msrno;
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unsigned int cpu_idx;
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#if CONFIG(LOGICAL_CPUS)
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u32 siblings;
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#endif
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disable_cache();
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/* Enable access to AMD RdDram and WrDram extension bits */
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msr = rdmsr(SYSCFG_MSR);
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msr.lo |= SYSCFG_MSR_MtrrFixDramModEn;
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn;
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wrmsr(SYSCFG_MSR, msr);
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/*
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* BSP: make a0000-bffff UC, c0000-fffff WB,
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* same as OntarioApMtrrSettingsList for APs
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*/
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msr.lo = msr.hi = 0;
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wrmsr(MTRR_FIX_16K_A0000, msr);
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msr.lo = msr.hi = 0x1e1e1e1e;
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wrmsr(MTRR_FIX_64K_00000, msr);
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wrmsr(MTRR_FIX_16K_80000, msr);
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for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++)
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wrmsr(msrno, msr);
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msr = rdmsr(SYSCFG_MSR);
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msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn;
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msr.lo |= SYSCFG_MSR_MtrrFixDramEn;
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wrmsr(SYSCFG_MSR, msr);
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x86_mtrr_check();
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x86_enable_cache();
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/* zero the machine check error status registers */
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msr = rdmsr(IA32_MCG_CAP);
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num_banks = msr.lo & MCA_BANKS_MASK;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < num_banks; i++)
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wrmsr(IA32_MC0_STATUS + (i * 4), msr);
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/* Enable the local CPU APICs */
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setup_lapic();
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#if CONFIG(LOGICAL_CPUS)
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siblings = cpuid_ecx(0x80000008) & 0xff;
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if (siblings > 0) {
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msr = rdmsr_amd(CPU_ID_FEATURES_MSR);
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msr.lo |= 1 << 28;
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wrmsr_amd(CPU_ID_FEATURES_MSR, msr);
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msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR);
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msr.hi |= 1 << (33 - 32);
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wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
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}
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printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
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#endif
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/* DisableCf8ExtCfg */
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msr = rdmsr(NB_CFG_MSR);
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msr.hi &= ~(1 << (46 - 32));
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wrmsr(NB_CFG_MSR, msr);
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if (CONFIG(HAVE_SMI_HANDLER)) {
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cpu_idx = cpu_info()->index;
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printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
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/* Set SMM base address for this CPU */
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msr = rdmsr(SMM_BASE_MSR);
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msr.lo = SMM_BASE - (cpu_idx * 0x400);
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wrmsr(SMM_BASE_MSR, msr);
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/* Enable the SMM memory window */
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msr = rdmsr(SMM_MASK_MSR);
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msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
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wrmsr(SMM_MASK_MSR, msr);
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}
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/* Write protect SMM space with SMMLOCK. */
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msr = rdmsr(HWCR_MSR);
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msr.lo |= (1 << 0);
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wrmsr(HWCR_MSR, msr);
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}
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static struct device_operations cpu_dev_ops = {
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.init = model_15_init,
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};
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static const struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_AMD, 0x630f00 }, /* KV-A0 */
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{ X86_VENDOR_AMD, 0x630f01 }, /* KV-A1 */
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{ 0, 0 },
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};
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static const struct cpu_driver model_15 __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@ -1,45 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* udelay() implementation for SMI handlers
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* This is neat in that it never writes to hardware registers, and thus does not
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* modify the state of the hardware while servicing SMIs.
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*/
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#include <cpu/x86/msr.h>
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#include <cpu/amd/msr.h>
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#include <cpu/x86/tsc.h>
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#include <delay.h>
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#include <stdint.h>
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void udelay(uint32_t us)
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{
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uint8_t fid, did, pstate_idx;
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uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks;
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msr_t msr;
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const uint64_t tsc_base = 100000000;
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/* Get initial timestamp before we do the math */
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tsc_start = rdtscll();
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/* Get the P-state. This determines which MSR to read */
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msr = rdmsr(PS_STS_REG);
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pstate_idx = msr.lo & 0x07;
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/* Get FID and VID for current P-State */
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msr = rdmsr(PSTATE_0_MSR + pstate_idx);
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/* Extract the FID and VID values */
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fid = msr.lo & 0x3f;
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did = (msr.lo >> 6) & 0x7;
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/* Calculate the CPU clock (from base freq of 100MHz) */
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tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
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/* Now go on and wait */
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tsc_wait_ticks = (tsc_clock / 1000000) * us;
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do {
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tsc_now = rdtscll();
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} while (tsc_now - tsc_wait_ticks < tsc_start);
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}
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@ -2,7 +2,6 @@
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config CPU_AMD_PI
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bool
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default y if CPU_AMD_PI_00630F01
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default y if CPU_AMD_PI_00730F01
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default n
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select ARCH_ALL_STAGES_X86_32
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@ -38,5 +37,4 @@ config DCACHE_BSP_STACK_SIZE
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endif # CPU_AMD_PI
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source "src/cpu/amd/pi/00630F01/Kconfig"
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source "src/cpu/amd/pi/00730F01/Kconfig"
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@ -1,4 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01
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subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01
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