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mb/intel/icelake_rvp: Move CNVi ASL entry from static DSDT to dynamic SSDT generation

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This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/icelake

Change-Id: I21d3818ac9e384b0dbaa330d231022bdb8b8a547
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This commit is contained in:
Subrata Banik
2018-11-06 17:07:01 +05:30
parent 26072787e0
commit 2df5abc53b
5 changed files with 9 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/mainboard/intel/icelake_rvp/variants/icl_u/devicetree.cb
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@@ -95,7 +95,10 @@ chip soc/intel/icelake
device pci 12.6 off end # GSPI #2
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on end # CNVi wifi
chip drivers/intel/wifi
register "wake" = "GPE0_PME_B0"
device pci 14.3 on end # CNVi wifi
end
device pci 14.5 on end # SDCard
device pci 15.0 on end # I2C #0
device pci 15.1 on end # I2C #1

5
src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb
View File

@@ -79,7 +79,10 @@ chip soc/intel/icelake
device pci 12.6 off end # GSPI #2
device pci 14.0 on end # USB xHCI
device pci 14.1 off end # USB xDCI (OTG)
device pci 14.3 on end # CNVi wifi
chip drivers/intel/wifi
register "wake" = "GPE0_PME_B0"
device pci 14.3 on end # CNVi wifi
end
device pci 14.5 on end # SDCard
device pci 15.0 on end # I2C 0
device pci 15.1 on end # I2C #1

32
src/soc/intel/icelake/acpi/cnvi.asl
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@@ -1,32 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2018 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <soc/pm.h>
/* CNVi Controller 0:14.3 */
Device (CNVI) {
Name(_ADR, 0x00140003)
Name (_S3D, 3) /* D3 supported in S3 */
Name (_S0W, 3) /* D3 can wake device in S0 */
Name (_S3W, 3) /* D3 can wake system from S3 */
Name (_PRW, Package() { PME_B0_EN_BIT, 3 })
Method (_STA, 0)
{
Return (0xF)
}
}

3
src/soc/intel/icelake/acpi/southbridge.asl
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@@ -56,8 +56,5 @@
/* PCI _OSC */
#include <soc/intel/common/acpi/pci_osc.asl>
/* CNVi */
#include "cnvi.asl"
/* GBe 0:1f.6 */
#include "pch_glan.asl"

1
src/soc/intel/icelake/chip.h
View File

@@ -20,6 +20,7 @@
#include <drivers/i2c/designware/dw_i2c.h>
#include <intelblocks/gspi.h>
#include <stdint.h>
#include <soc/gpe.h>
#include <soc/gpio.h>
#include <soc/pch.h>
#include <soc/gpio_defs.h>