soc/intel/{tigerlake,meteorlake}: Check ITBT FW version

The ensures that ITBT is ready to operate.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If60404a88208c632cd60e8aaa6ba70494eefbed2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77454
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

src/soc/intel/meteorlake/acpi/tcss.asl

@@ -455,6 +455,10 @@ Scope (\_SB.PCI0)
 				/* DMA0 is not in D3Cold now. */
 				\_SB.PCI0.TDM0.D3CE()  /* Enable DMA RTD3 */
 
+				If (\_SB.PCI0.TDM0.IF30 != 1) {
+					Return
+				}
+
 				Printf("Push TBT RPs to D3Cold together")
 				If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
 					/* Put RP0 to D3 cold. */
@@ -513,6 +517,10 @@ Scope (\_SB.PCI0)
 				/* DMA1 is not in D3Cold now */
 				\_SB.PCI0.TDM1.D3CE()  /* Enable DMA RTD3. */
 
+				If (\_SB.PCI0.TDM1.IF30 != 1) {
+					Return
+				}
+
 				Printf("Push TBT RPs to D3Cold together")
 				If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
 					/* Put RP2 to D3 cold. */

src/soc/intel/meteorlake/acpi/tcss_dma.asl

@@ -11,7 +11,8 @@ Field (DPME, AnyAcc, NoLock, Preserve)
 	, 6,
 	PMES, 1,        /* 15, PME_STATUS */
 	Offset(0xC8),   /* 0xC8, TBT NVM FW Revision */
-	,     31,
+	,     30,
+	IF30,  1,	/* ITBT FW Version Bit30 */
 	INFR,  1,       /* TBT NVM FW Ready */
 	Offset(0xEC),   /* 0xEC, TBT TO PCIE Register */
 	TB2P, 32,       /* TBT to PCIe */

src/soc/intel/tigerlake/acpi/tcss.asl

@@ -567,6 +567,10 @@ Scope (\_SB.PCI0)
 				/* DMA0 is not in D3Cold now. */
 				\_SB.PCI0.TDM0.D3CE()  /* Enable DMA RTD3 */
 
+				If (\_SB.PCI0.TDM0.IF30 != 1) {
+					Return
+				}
+
 				Printf("Push TBT RPs to D3Cold together")
 				If (\_SB.PCI0.TRP0.VDID != 0xFFFFFFFF) {
 					/* Put RP0 to D3 cold. */
@@ -622,6 +626,10 @@ Scope (\_SB.PCI0)
 				/* DMA1 is not in D3Cold now */
 				\_SB.PCI0.TDM1.D3CE()  /* Enable DMA RTD3. */
 
+				If (\_SB.PCI0.TDM1.IF30 != 1) {
+					Return
+				}
+
 				Printf("Push TBT RPs to D3Cold together")
 				If (\_SB.PCI0.TRP2.VDID != 0xFFFFFFFF) {
 					/* Put RP2 to D3 cold. */

src/soc/intel/tigerlake/acpi/tcss_dma.asl

@@ -11,7 +11,8 @@ Field (DPME, AnyAcc, NoLock, Preserve)
 	, 6,
 	PMES, 1,        /* 15, PME_STATUS */
 	Offset(0xC8),   /* 0xC8, TBT NVM FW Revision */
-	,     31,
+	,     30,
+	IF30,  1,       /* ITBT FW Version Bit30 */
 	INFR,  1,       /* TBT NVM FW Ready */
 	Offset(0xEC),   /* 0xEC, TBT TO PCIE Register */
 	TB2P, 32,       /* TBT to PCIe */