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chromeos: update old boards to use lb_add_gpios notation

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Instead of manually filling out the lb_gpios struct,
use the newer lb_add_gpios notation, which is more
compact and less error-prone.

BUG=b:124141368
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
BRANCH=none

Change-Id: I90795f32be5de881c94519933f36127098c184df
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32031
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Joel Kitching
2019-03-23 12:41:04 +08:00
committed by Patrick Georgi
parent f7f41a663f
commit 2e1f65545f
11 changed files with 164 additions and 393 deletions
Download Patch File Download Diff File Expand all files Collapse all files

56
src/mainboard/intel/baskingridge/chromeos.c
View File

@@ -26,52 +26,25 @@
#if ENV_RAMSTAGE
#include <boot/coreboot_tables.h>
#define GPIO_COUNT 6
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct device *dev = pcidev_on_root(0x1f, 0);
u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
struct lb_gpio chromeos_gpios[] = {
/* Write Protect: GPIO22 */
{0, ACTIVE_LOW, get_write_protect_state(), "write protect"},
if (!gpio_base)
return;
/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
{69, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
u32 gp_lvl = inl(gpio_base + GP_LVL);
u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
/* Hard code the lid switch GPIO to open. */
{-1, ACTIVE_HIGH, 1, "lid"},
gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
gpios->count = GPIO_COUNT;
/* Power Button */
{-1, ACTIVE_HIGH, 0, "power"},
/* Write Protect: GPIO22 */
gpios->gpios[0].port = 0;
gpios->gpios[0].polarity = ACTIVE_LOW;
gpios->gpios[0].value = (gp_lvl >> 22) & 1;
strncpy((char *)gpios->gpios[0].name,"write protect",
GPIO_MAX_NAME_LENGTH);
/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
gpios->gpios[1].port = 69;
gpios->gpios[1].polarity = ACTIVE_HIGH;
gpios->gpios[1].value = (gp_lvl3 >> (69-64)) & 1;
strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
/* Hard code the lid switch GPIO to open. */
gpios->gpios[3].port = -1;
gpios->gpios[3].polarity = ACTIVE_HIGH;
gpios->gpios[3].value = 1;
strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
/* Power Button */
gpios->gpios[4].port = -1;
gpios->gpios[4].polarity = ACTIVE_HIGH;
gpios->gpios[4].value = 0;
strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
/* Did we load the VGA option ROM? */
gpios->gpios[5].port = -1;
gpios->gpios[5].polarity = ACTIVE_HIGH;
gpios->gpios[5].value = gfx_get_init_done();
strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
/* Did we load the VGA option ROM? */
{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
#endif
@@ -86,7 +59,8 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void)
{
return 0;
/* Write protect is active low, so invert it here */
return !get_gpio(22);
}
static const struct cros_gpio cros_gpios[] = {