superio: Add ASpeed AST2400
Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Signed-off-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/23135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
committed by
Patrick Rudolph
parent
3d84038d57
commit
2e1fea408d
@@ -2,6 +2,7 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Nico Huber <nico.h@gmx.de>
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* Copyright (C) 2017-2018 Eltan B.V.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@@ -48,6 +49,12 @@ void pnp_enter_conf_mode_a0a0(struct device *dev)
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outb(0xa0, dev->path.pnp.port);
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}
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void pnp_enter_conf_mode_a5a5(struct device *dev)
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{
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outb(0xa5, dev->path.pnp.port);
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outb(0xa5, dev->path.pnp.port);
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}
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void pnp_exit_conf_mode_aa(struct device *dev)
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{
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outb(0xaa, dev->path.pnp.port);
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@@ -96,6 +103,11 @@ const struct pnp_mode_ops pnp_conf_mode_a0a0_aa = {
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.exit_conf_mode = pnp_exit_conf_mode_aa,
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};
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const struct pnp_mode_ops pnp_conf_mode_a5a5_aa = {
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.enter_conf_mode = pnp_enter_conf_mode_a5a5,
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.exit_conf_mode = pnp_exit_conf_mode_aa,
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};
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const struct pnp_mode_ops pnp_conf_mode_870155_aa = {
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.enter_conf_mode = pnp_enter_conf_mode_870155aa,
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.exit_conf_mode = pnp_exit_conf_mode_0202,
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