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soc/intel/xeon_sp: Reserve MMIO for Gen1 SoC

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For Gen1 SoCs, the range starting from the end of VTd BAR to the end
of 32-bit domain MMIO resource window is reserved for unknown devices.
Get them reserved.

TEST=Build and boot on intel/archercity CRB

Change-Id: Ie133fe3173ce9696769c7247bd2524c7b21b1cf8
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Shuo Liu 2024-06-19 06:48:45 +08:00 committed by Lean Sheng Tan
parent 0a6f5188e8
commit 2eb9d5ed62
2 changed files with 26 additions and 3 deletions
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8
src/soc/intel/xeon_sp/chip_gen1.c
View File

@ -7,6 +7,7 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <soc/pci_devs.h> #include <soc/pci_devs.h>
#include <intelblocks/acpi.h> #include <intelblocks/acpi.h>
#include <intelblocks/vtd.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <soc/chip_common.h> #include <soc/chip_common.h>
#include <soc/soc_util.h> #include <soc/soc_util.h>
@ -54,6 +55,13 @@ static void iio_pci_domain_read_resources(struct device *dev)
if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit) if (sr->PciResourceMem64Base < sr->PciResourceMem64Limit)
domain_mem_window_from_to(dev, index++, domain_mem_window_from_to(dev, index++,
sr->PciResourceMem64Base, sr->PciResourceMem64Limit + 1); sr->PciResourceMem64Base, sr->PciResourceMem64Limit + 1);
/* Declare domain reserved MMIO */
uint64_t reserved_mmio = sr->VtdBarAddress + vtd_probe_bar_size(pcidev_on_root(0, 0));
if ((reserved_mmio >= sr->PciResourceMem32Base) &&
(reserved_mmio <= sr->PciResourceMem32Limit))
mmio_range(dev, index++, reserved_mmio,
sr->PciResourceMem32Limit - reserved_mmio + 1);
} }
/* /*

21
src/soc/intel/xeon_sp/spr/ioat.c
View File

@ -8,6 +8,7 @@
#include <defs_iio.h> #include <defs_iio.h>
#include <hob_iiouds.h> #include <hob_iiouds.h>
#include <intelblocks/acpi.h> #include <intelblocks/acpi.h>
#include <intelblocks/vtd.h>
#include <soc/acpi.h> #include <soc/acpi.h>
#include <IioPcieConfigUpd.h> #include <IioPcieConfigUpd.h>
@ -29,7 +30,7 @@ static struct device_operations ioat_domain_ops = {
#endif #endif
}; };
static void create_ioat_domain(const union xeon_domain_path dp, struct bus *const upstream, static struct device *const create_ioat_domain(const union xeon_domain_path dp, struct bus *const upstream,
const unsigned int bus_base, const unsigned int bus_limit, const unsigned int bus_base, const unsigned int bus_limit,
const resource_t mem32_base, const resource_t mem32_limit, const resource_t mem32_base, const resource_t mem32_limit,
const resource_t mem64_base, const resource_t mem64_limit, const resource_t mem64_base, const resource_t mem64_limit,
@ -66,6 +67,8 @@ static void create_ioat_domain(const union xeon_domain_path dp, struct bus *cons
if (mem64_base <= mem64_limit) if (mem64_base <= mem64_limit)
domain_mem_window_from_to(domain, index++, mem64_base, mem64_limit + 1); domain_mem_window_from_to(domain, index++, mem64_base, mem64_limit + 1);
return domain;
} }
void create_ioat_domains(const union xeon_domain_path path, void create_ioat_domains(const union xeon_domain_path path,
@ -130,6 +133,18 @@ void create_ioat_domains(const union xeon_domain_path path,
mem64_limit = sr->PciResourceMem64Limit; mem64_limit = sr->PciResourceMem64Limit;
bus_base = sr->BusBase; bus_base = sr->BusBase;
bus_limit = bus_base; bus_limit = bus_base;
create_ioat_domain(path, bus, bus_base, bus_limit, sr->PciResourceMem32Base, sr->PciResourceMem32Limit, struct device *const dev = create_ioat_domain(path, bus, bus_base, bus_limit,
mem64_base, mem64_limit, DOMAIN_TYPE_DINO, pci_segment_group); sr->PciResourceMem32Base, sr->PciResourceMem32Limit,
mem64_base, mem64_limit, DOMAIN_TYPE_DINO, pci_segment_group);
/* Declare domain reserved MMIO */
uint64_t reserved_mmio = sr->VtdBarAddress + vtd_probe_bar_size(pcidev_on_root(0, 0));
if ((reserved_mmio >= sr->PciResourceMem32Base) &&
(reserved_mmio <= sr->PciResourceMem32Limit)) {
int index = 0;
for (struct resource *res = dev->resource_list; res; res = res->next)
index++;
mmio_range(dev, index, reserved_mmio,
sr->PciResourceMem32Limit - reserved_mmio + 1);
}
} }